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Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices

  • US 5,422,892 A
  • Filed: 08/02/1994
  • Issued: 06/06/1995
  • Est. Priority Date: 11/23/1992
  • Status: Expired due to Term
First Claim
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1. A method for testing a semiconductor device comprising the steps of:

  • a) sending an address signal from a device tester to a device under test having plural storage locations;

    b) storing a test data signal in a register located in said device tester;

    c) sending said test data signal from said device tester to parallel compare circuitry;

    d) duplicating said test data signal in said parallel compare circuitry and storing said duplicated test data signals in said device under test in plural storage locations selected by said address signal;

    e) re-addressing said plural storage locations having said duplicated test data signals stored therein and reading out said stored duplicated test data signals from said plural storage locations to said parallel compare circuitry in response to a read signal;

    f) comparing read out said stored duplicated test data signals with one another in said parallel compare circuitry and producing a parallel compare circuitry output signal having a first state if all of said stored duplicated test data signals are at a similar voltage level corresponding to a same logic level or a second state if at least one of said stored duplicated test data signals has a voltage which corresponds to a different logic level as the others of said stored duplicated test data signals; and

    g) sending said parallel compare circuitry output signal to said device tester.

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