Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices

• US 5,422,892 A
• Filed: 08/02/1994
• Issued: 06/06/1995
• Est. Priority Date: 11/23/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Singh, Inderjit, Rousey, James E., Hii, Francis
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/284,911
• Time in Patent Office: 308 Days
• Field of Search: 371/24, 371/21.1, 371/21.2, 371/21.5, 371/21.3, 371/27
• US Class Current: 714/735
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.

Claims

1. A method for testing a semiconductor device comprising the steps of:

a) sending an address signal from a device tester to a device under test having plural storage locations;

b) storing a test data signal in a register located in said device tester;

c) sending said test data signal from said device tester to parallel compare circuitry;

d) duplicating said test data signal in said parallel compare circuitry and storing said duplicated test data signals in said device under test in plural storage locations selected by said address signal;

e) re-addressing said plural storage locations having said duplicated test data signals stored therein and reading out said stored duplicated test data signals from said plural storage locations to said parallel compare circuitry in response to a read signal;

f) comparing read out said stored duplicated test data signals with one another in said parallel compare circuitry and producing a parallel compare circuitry output signal having a first state if all of said stored duplicated test data signals are at a similar voltage level corresponding to a same logic level or a second state if at least one of said stored duplicated test data signals has a voltage which corresponds to a different logic level as the others of said stored duplicated test data signals; and

g) sending said parallel compare circuitry output signal to said device tester.

2. The method of claim 1 wherein said duplicating step includes:

duplicating said test data signal by enabling multiple paths through said parallel compare circuitry in response to a write signal; and

storing said duplicated test data signals in said plural storage locations in said device under test in response to said write signal.

3. The method of claim 2 wherein said comparing step further includes:

disabling said multiple paths through said parallel compare circuitry in response to said read signal.

4. The method of claim 1 further comprising the step of:

comparing said parallel comparator circuitry output signal with said stored register test data signal to produce a test result signal which is a pass state if said parallel comparator circuitry output signal matches said stored register test data signal or which is a fail state if said parallel comparator circuitry output signal is different than said stored register test data signal.

5. A test system comprising:

a socket for coupling to a particular device under test, said socket having plural data leads, said particular device under test having plural data leads and plural storage locations;

a device tester coupled to said socket, said device tester including;

a register,

an address bus,

control circuitry for sending address signals from said device tester over the address bus to said socket and for storing data signals created by said control circuitry in the register in said device tester, and

transceiver circuitry coupled to said control circuitry for sending said created data signals via a parallel compare circuitry data lead from said device tester to a parallel compare circuitry;

said test system further comprising;

said parallel compare circuitry coupled to said transceiver circuitry and to said plural data leads of said socket for sending said created data signals from said transceiver circuit to said plural storage locations in said device under test in response to address signals sent from the control circuit, said parallel compare circuitry reading out stored data signals from said plural storage locations in said device under test through said plural data leads of said socket and determining if one of said read out stored data signals on said socket plural data leads is different from other read out stored data signals on said socket plural data leads, then said parallel compare circuitry producing a parallel compare output signal on said parallel compare data lead; and

said transceiver circuitry comparing said data signal from said register with said parallel compare output signal and producing a pass signal if said parallel compare output signal matches said register data signal, a fail signal if said register data signal is different than said parallel compare output signal.

6. The test system of claim 5 wherein said parallel compare circuitry comprises:

one or more gating transistors responsive to a control signal from said control circuitry for coupling said transceiving circuitry to said socket when data is sent to said socket, and for disabling a path between said socket and said transceiving circuitry when data is sent back from said socket to said transceiving circuitry; and

a comparator coupled to said socket plural data leads for comparing said stored data signals on said socket plural data leads to each other, then said comparator producing said parallel compare output signal on said parallel compare data lead responsive to said comparison.