Fuzzy logic controller with optimized storage organization

• US 5,422,979 A
• Filed: 03/07/1994
• Issued: 06/06/1995
• Est. Priority Date: 09/11/1991
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Eichfeld, Herbert, Lohner, Michael
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Dorvil, Richemond
• Application Number:
  US08/204,318
• Time in Patent Office: 456 Days
• Field of Search: 395/3, 395/61, 395/900, 395/51
• US Class Current: 706/4
• CPC Class Codes: G05B 13/0275 using fuzzy logic only
• CPC Class Codes: G06F 1/0356 by using two or more smaller tables, e.g. addressed by parts of the argument
• CPC Class Codes: G06N 7/04 Physical realisation
• CPC Class Codes: Y10S 706/90 Fuzzy logic

Abstract

In a fuzzy logic controller, numbers (NI) for linguistic values of the input signal (I1) and first and further parts of input relevance functions (ZL, ZH) of the input signal (I1) can be stored per input signal (I1 . . . I4) in an input memory (I1MEM . . . I4MEM). The numbers for the linguistic values can be fed directly and via incrementing devices (INC1 . . . INC4) to a regulating decoder (RDEC) through a number multiplexer (MUX1a . . . MUX4a), the regulating decoder supplying addresses for a downstream output memory (OMEM). An output signal of the output memory (OMEM) can be fed directly and the first and further parts of the input relevance functions can be fed via relevance function multiplexers (MUX1b . . . MUX4b) to a minimum/maximum circuit (MINMAX). The fuzzy logic controller is distinguished in particular by a very low storage space requirement and is therefore suitable in particular for fuzzy logic controllers with on-chip memories.

Claims

1. A fuzzy logic controller, comprising:

a regulating memory for fuzzification connected to a regulating decoder and a minimum/maximum circuit for inference formation and a defuzzification circuit connected downstream of the minimum/maximum circuit;

the regulating memory having f input memories and an output memory, for each input memory an input signal being fed via a respective buffer/decoding circuit to a respective input of a respective input memory;

each input signal having an input resolution e and each buffer/decoding circuit forming 2^e addresses for the respective input memory;

a respective input memory of the f input memories having stored numbers for linguistic values of a respective input signal and function values of a first and h-1 further input relevance functions, h representing a degree of overlap of input assignment functions;

for each input memory a number for a first relevant linguistic value of a respective input signal being fed directly and numbers for further relevant linguistic values of the respective input signal being fed via a respective incrementing device to inputs of a respective number multiplexer and being successively switched through by the respective number multiplexer in dependence on a respective multiplexer control signal to a respective input of the regulating decoder;

the function values of a first and of h-1 further input relevance functions being successively fed in dependence on the respective multiplexer control signal via a respective relevance function multiplexer to a minimum operation element of the minimum/maximum circuit; and

numbers for linguistic values of an output signal being assigned by rules stored in the regulating decoder from numbers for the relevant linguistic values of the respective input signal and these numbers for linguistic values of an output signal serving as addresses for a downstream output memory that is connected to the regulating decoder, said downstream memory containing values for relevance functions of the output signal and said downstream memory having an output connected via an output multiplexer to the minimum operation element of the minimum/maximum circuit.

2. The fuzzy logic controller as claimed in claim 1, wherein the degree of overlap is h=2, wherein each number multiplexer and each relevance function multiplexer are 1-of-2 multiplexers and the respective multiplexer control signals are only one bit wide and wherein in each of the incrementing devices there is respectively formed from the number for the first relevant linguistic value of the respective input signal, by addition of a one, only a number for a further relevant linguistic value from the selected address range of the respective input signal.

3. The fuzzy logic controller as claimed in claim 1, wherein the minimum/maximum circuit has f+1 inputs, which are also inputs of the minimum operation element and wherein one output of the minimum operation is connected to a first input of a maximum operation element and an output signal of the maximum operation element, is delayed by means of a delay flipflop and subsequently is fed via a first AND gate to a second input of the maximum operation element or via a second AND gate to the defuzzification circuit.

4. The fuzzy logic controller as claimed in claim 1, wherein the regulating decoder is a memory.

5. The fuzzy logic controller as claimed in claim 1, wherein the fuzzy logic controller is located together with the regulating memory on a common semiconductor chip.

6. The fuzzy logic controller as claimed in claim 1, wherein the fuzzy logic controller is monolithically integrated with a conventional multipurpose controller.