Method and means for fast writing of run length coded bit strings into bit mapped memory and the like

• US 5,422,995 A
• Filed: 03/16/1993
• Issued: 06/06/1995
• Est. Priority Date: 03/30/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Aoki, Yutaka, Gohda, Yuji, Rackley, Darwin P.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/032,084
• Time in Patent Office: 812 Days
• Field of Search: 395/128, 395/133, 395/141, 395/200, 395/162, 395/163, 395/121, 395/122, 395/123, 395/126, 395/127, 395/133, 395/134, 395/135, 395/138, 395/162, 395/164, 395/166, 358/261.1, 358/261.2, 358/261.4, 358/500, 364/255.1, 364/256.8, 364/955, 364/961.3
• US Class Current: 345/545
• CPC Class Codes: G06T 9/005 Statistical coding, e.g. Huffman, run length coding
• CPC Class Codes: H03M 7/46 Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

Abstract

A method and means which upon detecting indicia embedded in a decoded run length coded bit string skips over a range of bit memory mapped addresses thus reducing the number of write operations into a counterpart bit mapped memory. The coded indicia include portions which specify a skip and a skip range for storage locations in said bit mapped memory.

Claims

1. In a system having a symbol addressable memory, a source of run length coded symbol strings, means for writing symbol strings from the source into counterpart memory addresses in raster scan line order, and means for reading and displaying the contents of memory addresses in raster scan line order, a method for rapidly writing said symbol adressable memory comprising the steps of:

(a) embedding coded indicia descriptive of run attributes in predetermined positions in each symbol string in said source, said indicia including a start of string, symbol string length, and symbol similarity or dissimilarity; and

(b) responsive to commands for writing at least one symbol string from said source into said symbol addressable memory, ascertaining the run attributes from the coded indicia embedded in the symbol string, and, either writing said symbol string in raster scan line order into said symbol addressable memory if the indicia indicate at least two of the string symbols are dissimilar, or, skipping memory addresses in raster scan line order counterpart to symbols in the string if the indicia indicate the string symbols are similar.

5. A data processing system comprising a display apparatus, an external storage apparatus for storing display data represented by run length codes, a CPU for reading out the display data from the external storage apparatus, a system memory having areas for storing the display data read out from the external storage apparatus, and a bit map memory for storing the display data in storage locations corresponding to display positions of the display apparatus, wherein said system further comprises:

means for decoding a display data in the system memory and writing the decoded display data to the bit map memory; and

a video controller including said decoding means for transmitting a video signal to said display apparatus based on the display data in the bit map memory and the storage locations for the display data, in response to a predetermined code in a run length data flow,

said decoding and writing means, responsive to coded indicia in a bit string defining a string where at least two bits have dissimilar values, writing the string of dissimilar bit values into the bit map memory at a first bit rate, and responsive to coded indicia in a bit string defining a string of the same value bits, skipping over a predetermined range of storage locations in the bit map memory at a second bit rate higher than the first bit rate.

2. The method according to claim 6, wherein said writing step occurring at a first synchronous rate of accessing memory addresses in raster scan line order, and further wherein said skipping step includes disabling the writing means over a predetermined number of memory addresses, said disablement of said writing means effectuating a synchronous rate for accessing memory addresses in raster scan line order higher than the first synchronous rate.

3. A method as recited in claim 2 wherein said coded indicia comprises a skip entry portion and a skip range portion, said skip range portion specifies storage locations in said symbol addressable memory.

4. A method as recited in claim 3 wherein said skip range portion specifies number of pixels and number of display lines to be skipped.

6. A system as recited in claim 5 wherein said coded indicia comprises a skip entry portion and a skip range portion, said skip range portion specifies storage locations in said symbol addressable memory.

7. A system as recited in claim 6 wherein said skip range portion specifies number of pixels and number of display lines to be skipped.