Video memory with flash fill

• US 5,422,998 A
• Filed: 11/15/1993
• Issued: 06/06/1995
• Est. Priority Date: 11/15/1993
• Status: Expired due to Term

• Current Assignee: Animedia Company LLC (Intellectual Ventures LLC)
• Original Assignee: Jed Margolin
• Inventors: Margolin, Jed
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US08/153,200
• Time in Patent Office: 568 Days
• Field of Search: 395/164-166, 395/425, 395/400, 345/185, 345/189, 345/190, 365/230.01, 365/230.03, 365/230.05, 365/230.08, 365/230.09, 365/189.01, 365/189.04, 365/189.05
• US Class Current: 345/519
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A single-chip semiconductor memory device optimized for high performance flat-shaded polygon video systems consists of a RAM with flash fill circuitry whereby the Start and End addresses are specified for a given row; the data within this range are read, modified, and written back to the memory in parallel thereby requiring a maximum of three memory cycles to fill a line segment independent of the length of the line. The data are modified according to a function between a color register and the data already present in the memory array, the functions being: AND, OR, EXCLUSIVE OR, or REPLACE.

Claims

1. An apparatus for addressing and modifying data in a row addressable memory which stores a plurality of lines of information and is placed on an integrated circuit, said row addressable memory receiving row address, color data, start address, end address, and logic function data, said start address and said end address defining a portion of data at said row address to be modified according to said color data and said logic function data, wherein modification of said portion of data is to be performed simultaneously, and said start address and said end address to permit as a maximum size an entire row of said row addressable memory corresponding to an entire line of displayed video, said apparatus on said integrated circuit comprising:

a memory array with row address circuitry for selecting a row in said memory array, wherein an entire row of memory cell data, of said row, being simultaneously available during read operations, and said entire row of memory cells being simultaneously available during write operations;

a data latch means for storing said entire row of memory cell data of said row of said memory array;

a fill unit with a plurality of stages corresponding to all memory cell addresses in said row of said memory array, each fill unit stage employing one address compare unit and an individual bit processing unit for each bit plane of said memory array, said address compare unit employing a first address comparator to compare said start address with a fixed address corresponding to said fill unit stage, a second address comparator to compare said end address with said fixed address of said fill unit stage, and a combinatorial logic circuit to combine outputs of said first address comparator and said second address comparator, each said bit processing unit employing logic gates which modify data from said data latch means according to said logic function data, said color data, and the combinatorial logic circuit, wherein when said fixed address of said stage is greater than or equal to said start address and less than or equal to said end address, said data from said data latch means is modified according to said color data and said logic function data, otherwise said data from said data latch means is not modified.

2. An apparatus according to claim 1 wherein said memory cells are one transistor memory cells.

3. An apparatus according to claim 1 wherein each input gate of said first address comparator for a fixed address input bit with a logic low value comprises an AND gate means whose inputs are a corresponding bit from said start address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate means whose inputs are said corresponding bit from said start address and said output of said previous comparator gate of lesser weight.

4. An apparatus according to claim 1 wherein each input gate of said second address comparator for a fixed address input bit with a logic low value comprises an AND gate means whose inputs are a corresponding bit from said end address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate means whose inputs are said corresponding bit from said end address and said output of said previous comparator gate of lesser weight.

5. An apparatus according to claim 1 wherein the bit processing unit comprises logic gates which modify said data from said data latch means, said logic gates comprising AND gate means, OR gate means, exclusive OR gate means, and direct input from said color data.

6. An apparatus for addressing and modifying data in a row addressable memory which stores a plurality of lines of information and is placed on an integrated circuit, said row addressable memory receiving row address, color data, start address, end address, and logic function data, said start address and said end address defining a portion of data at said row address to be modified according to said color data and said logic function data, wherein modification of said portion of data is to be performed simultaneously, and said start address and said end address to permit as a maximum size an entire row of said row addressable memory corresponding to an entire line of displayed video, said apparatus on said integrated circuit comprising:

a memory array with row address circuitry for selecting a row in said memory array, wherein an entire row of memory cell data, of said row, being simultaneously available during read operations, and said entire row of memory cells being simultaneously available during write operations;

a memory data latch means for storing said entire row of memory cell data of said row of said memory array;

an address compare unit with a plurality of address compare stages corresponding to all memory cell addresses in said row of said memory array, each address compare stage employing a first address comparator to compare said start address with a fixed address of said address compare stage, a second address comparator to compare said end address with said fixed address of said address compare stage and a combinatorial logic circuit to combine outputs of said first address comparator and said second address comparator, wherein when said fixed address of said address compare stage is greater than or equal to said start address and less than or equal to said end address an output of said combinatorial logic circuit is asserted;

one or more bit processing units for each address compare unit, each said bit processing unit comprising logic gates which modify data from the memory data latch means according to said logic function data, said color data, and said combinatorial logic circuit, wherein when an output of a corresponding stage of said combinatorial logic circuit is asserted, said data from said memory data latch means is modified according to said color data and said logic function data, otherwise said data from said memory data latch means is not modified.

7. An apparatus according to claim 6 wherein said memory cells are one transistor memory cells.

8. An apparatus according to claim 6 wherein each input gate of said first address comparator for a fixed address input bit with a logic low value comprises an AND gate means whose inputs are a corresponding bit from said start address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate means whose inputs are said corresponding bit from said start address and said output of said previous comparator gate of lesser weight.

9. An apparatus according to claim 6 wherein each input gate of said second address comparator for a fixed address input bit with a logic low value comprises an AND gate means whose inputs are a corresponding bit from the end address and an output of the previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate means whose inputs are said corresponding bit from said end address and said output of said previous comparator gate of lesser weight.

10. An apparatus according to claim 6 wherein the bit processing unit comprises logic gates which modify said data from said memory data latch means, said logic gates comprising AND gate means, OR gate means, exclusive OR gate means, and direct input from said color data.

11. A comparator for comparing a variable address with a fixed address comprising:

an arrangement of logic gates in which each input gate for a fixed address input bit with a logic low value comprises an AND gate means whose inputs are a corresponding bit from said variable address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate means whose inputs are said corresponding bit from said variable address and said output of said previous comparator gate of lesser weight.

12. An apparatus for addressing and modifying data in a row addressable memory which stores a plurality of lines of information and is placed on an integrated circuit, said row addressable memory receiving row address, color data, start address, end address, and logic function data, said start address and said end address defining a portion of data at said row address to be modified according to said color data and said logic function data, wherein modification of said portion of data is to be performed simultaneously, and said start address and said end address to permit, as a maximum size, an entire row of said row addressable memory corresponding to an entire line of displayed video, said apparatus comprising:

a memory array with row address circuitry for selecting a row in said memory array, wherein an entire row of memory cell data, of said row, being simultaneously available during read operations, and said entire row of memory cells being simultaneously available during write operations;

a data latch for storing said entire row of memory cell data of said row of said memory array;

a fill unit with a plurality of stages corresponding to all memory cell addresses in said row of said memory array, each fill unit stage employing one address compare unit and an individual bit processing unit for each bit plane of said memory array, said address compare unit employing a first address comparator to compare said start address with a fixed address corresponding to said fill unit stage, a second address comparator to compare said end address with said fixed address of said fill unit stage, and a combinatorial logic circuit to combine outputs of said first address comparator and said second address comparator, each said bit processing unit employing logic gates which modify data from said data latch according to said logic function data, said color data, and the combinatorial logic circuit, wherein when said fixed address of said stage is greater than or equal to said star address and less than or equal to said end address, said data from said data latch is modified according to said color data and said logic function data, otherwise said data from said data latch is not modified.

13. An apparatus according to claim 12 wherein said memory cells are comprised of one transistor memory cells.

14. An apparatus according to claim 12 wherein each input gate of said first address comparator for a fixed address input bit with a logic low value comprises an AND gate whose inputs are a corresponding bit from said start address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate whose inputs are said corresponding bit from said start address and said output of said previous comparator gate of lesser weight.

15. An apparatus according to claim 12 wherein each input gate of said second address comparator for a fixed address input bit with a logic low value comprises an AND gate whose inputs are a corresponding bit from said end address and an output of a previous comparator gate of lesser weight, and each input gate for said fixed address input bit with a logic high value comprises an OR gate whose inputs are said corresponding bit from said end address and said output of said previous comparator gate of lesser weight.

16. An apparatus according to claim 12 wherein the bit processing unit comprises logic gates which modify said data from said data latch, said logic gates comprising an AND gate, an OR gate, an exclusive OR gate, and direct input from said color data.