Method for manufacturing a VDMOS transistor

• US 5,424,231 A
• Filed: 08/09/1994
• Issued: 06/13/1995
• Est. Priority Date: 08/09/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yang, Sheng-Hsing
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US08/287,950
• Time in Patent Office: 308 Days
• Field of Search: 437/6, 437/40, 437/42, 437/43, 437/913, 437/911, 437/149, 437/150, 148/DIG. 126, 148/DIG. 82
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor'"'"'s implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Claims

1. A method of producing a VDMOS transistor on a substrate of a first conductivity type, comprising the steps of:

(a) forming a drain electrode region of said first conductivity type in said substrate, the drain electrode region having a drain electrode region doping density;

(b) forming an epitaxial layer of said first conductivity type on said drain electrode region, the epitaxial layer having an epitaxial layer doping density which is lower than said drain electrode region doping density.

(c) forming a body region of a second conductivity type on said epitaxial layer;

(d) forming a source electrode region of said first conductivity type in said body region;

(e) forming a trench through said source electrode region and the body region, to reach said epitaxial layer;

(f) implanting impurities of said first conductivity type into a bottom surface of said trench to form an implanted region having an implanted region doping density;

(g) thermally diffusing said impurities of said step (f) and forming an oxide layer in said trench;

(h) forming a silicon nitride layer on said oxide layer said step (g);

(i) etching said bottom surface of said trench to reach said epitaxial layer;

(j) implanting impurities of said first conductivity type into said bottom surface of said trench to form a subsequent implanted region having a subsequent implanted region doping density which is higher than said implanted region doping density of said implanted region of said step (f);

(k) thermally diffusing said impurities of said step (j) and forming a subsequent oxide layer on said bottom of said trench;

(l) repeating said steps (i) to (k) at least once, while continuously increasing said subsequent implanted region doping density each time said step (j) is repeated;

(m) forming a gate electrode in said trench;

(n) forming an additional oxide layer on said substrate;

(o) forming metal vias in said additional oxide layer of said step (n); and

(p) forming metal contacts and wiring.

2. The method of claim 1, wherein said first conductivity type is N type and said second conductivity type is P type.

3. The method of claim 1, wherein said first conductivity type is P type and said second conductivity type is N type.

4. The method of claim 1, wherein said drain electrode region has a coefficient of drain electrode region electrical resistance between 0.005 Ω

-cm and 0.1 Ω

-cm.

5. The method of claim 1, wherein said epitaxial layer has a coefficient of epitaxial layer electrical resistance between 0.1 Ω

-cm and 100 Ω

-cm and an epitaxial layer thickness between 8 μ

m and 100 μ

m.

6. The method of claim 1, wherein said body region has a body region thickness between 3 μ

m and 4 μ

m.

7. A method of producing a VDMOS transistor on a substrate of a first type, comprising the steps of:

(a) forming a drain electrode region of a second conductivity type in said substrate, the drain electrode region having a drain electrode region doping density;

(b) forming an epitaxial layer of said second conductivity type on said drain electrode region, the epitaxial layer having an epitaxial layer doping density which is lower than said drain electrode region doping density;

(c) forming a sinker of said second conductivity type at a sinker position in said epitaxial layer, said sinker being connected to said drain electrode region to define an active region in said epitaxial layer;

(d) implanting impurities of said first conductivity type into an implanted region position in said active region to form a first conductivity type implanted region having a first conductivity type implanted region thickness less than an epitaxial layer thickness of said epitaxial layer;

(e) implanting impurities of said first conductivity type into a body region position in said first conductivity type implanted region to form a first conductivity type body region on said epitaxial layer, said first conductivity type body region having a doping density which is lower than a first conductivity type implanted region doping density of said first conductivity type implanted region;

(f) forming a source electrode region of said second conductivity type in said first conductivity type body region;

(g) forming a trench through said source electrode region and said first conductivity type body region, to reach said epitaxial layer;

(h) implanting impurities of said second conductivity type into a bottom surface of said trench to form a second conductivity type implanted region having a second conductivity type implanted region doping density;

(i) thermally diffusing said impurities of said step (h) and forming an oxide layer in said trench;

(j) forming a silicon nitride layer on said oxide layer of said step (i);

(k) etching said bottom surface of said trench to reach said epitaxial layer;

(l) implanting impurities of said second conductivity type into the bottom of said trench to form a subsequent second conductivity type implanted region having a subsequent second conductivity type implanted region doping density which is higher than said second conductivity type implanted region doping density of said second conductivity type implanted region of said step (h);

(m) thermally diffusing said impurities of said step (1) and forming a subsequent oxide layer on said bottom of said trench;

(n) repeating said steps (k) to (m) at least once, while continuously increasing said subsequent second conductivity type implanted region doping density each time said step (1) is repeated;

(o) forming a gate electrode in said trench;

(p) forming an additional oxide layer on said substrate;

(q) forming metal vias in said additional oxide layer of said step (p); and

(r) forming metal contacts and wiring.

8. The method of claim 7, wherein said first conductivity type is P type and said second conductivity type is N type.

9. The method of claim 7, wherein said first conductivity type is N type and said second conductivity type is P type.

10. The method of claim 7, wherein said drain electrode region has a coefficient of drain electrode region electrical resistance between 0.005 Ω

-cm and 0.1 Ω

-cm.

11. The method of claim 7, wherein said epitaxial layer has a coefficient of epitaxial layer electrical resistance between 0.1 Ω

-cm and 100 Ω

-cm and an epitaxial layer thickness between 8 μ

m and 100 μ

m.

12. The method of claim 7, wherein said body region has a body region thickness between 3 μ

m and 4 μ

m.