Method of forming vias through two-sided substrate

• US 5,424,245 A
• Filed: 01/04/1994
• Issued: 06/13/1995
• Est. Priority Date: 01/04/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gurtler, Richard W., Pearse, Jeffrey, Wilson, Syd R.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/177,350
• Time in Patent Office: 525 Days
• Field of Search: 257/774, 257/777, 437/209, 437/183
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73103 Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Abstract

An integrated circuit substrate (26) is formed with active circuit elements (24, 32) on first and second surfaces of the substrate. The active circuit elements are interconnected with though-substrate vias (28) to minimize signal routing and reduce propagation delay. The through-substrate vias may be formed with a plurality of holes (52) through the IC substrate. A dielectric layer (54) is deposited on the surface of the IC substrate and through the holes. A conductive layer (56) is deposited through the holes to form the through-substrate vias. The dielectric layer is removed from the surface of the IC substrate to leave the through-substrate vias isolated from the IC substrate by the dielectric layer. A second substrate (26) is formed as described and the two substrates are joined as a two-sided chip (21) with active circuit elements on both sides interconnected by through-substrate vias.

Claims

1. A method of forming through-substrate vias in a substrate, comprising the steps of:

forming a first hollow region through a first substrate;

depositing a first dielectric layer on a first surface of said first substrate and on inner surfaces of said first hollow region;

depositing a first conductive layer through said first hollow region to form a first through-substrate via;

removing said first conductive layer and said first dielectric layer from said first surface of said first substrate to leave said first through-substrate via isolated from said first substrate by said first dielectric layer;

forming a first IC device layer on said first surface of said first substrate with circuit nodes electrically coupled to the through-substrate vias;

forming a first interconnect layer on said first IC device layer;

forming first inter-chip interconnects on said first interconnect layer;

patterning a second dielectric layer on a second surface of said first substrate to provide access to said first through-substrate via; and

forming a first bump making contact to said first through-substrate via.

2. The method of claim 1 further including the steps of:

forming a second region through a second substrate;

depositing a third dielectric layer on a first surface of said second substrate and on inner surfaces of said second region;

depositing a second conductive layer through said second region;

removing said second conductive layer and said third dielectric layer from said first surface of said second substrate to leave a second through-substrate via isolated from said second substrate by said third dielectric layer;

forming a second IC device layer on said first surface of said second substrate with circuit nodes electrically coupled to the through-substrate vias;

forming a second interconnect layer on said second IC device layer;

forming second inter-chip interconnects on said second interconnect layer;

patterning a fourth dielectric layer on a second surface of said second substrate to provide access to said second through-substrate via;

forming a second bump making contact to said second through-substrate via; and

joining said first and second bumps of said first and second substrates to provide electrical connectivity between said first and second IC device layers.

3. A method of forming through-substrate vias in a substrate, comprising the steps of:

forming a first IC device layer on a first surface of a first substrate;

forming a first dielectric layer within said first IC device layer;

forming a first pad within said first IC device layer isolated from said first substrate by said first dielectric layer;

depositing a second dielectric layer on a second surface of said first substrate;

etching a first region through said first substrate;

depositing a third dielectric layer on said second dielectric layer and on inner surfaces of said first region for isolation;

selectively removing portions of said first, second and third dielectric layers to expose said first pad;

depositing a first conductive layer through said first region and contacting said first pad to form a first through-substrate via; and

selectively removing said first conductive layer from said second surface of said first substrate to provide electrical isolation for said first through-substrate via.

4. The method of claim 3 further including the steps of:

depositing a fourth dielectric layer on said second dielectric layer; and

forming a first bump making contact to said first through-substrate via.

5. The method of claim 4 further including the steps of:

forming a second IC device layer on a first surface of a second substrate;

forming a fifth dielectric layer within said second IC device layer;

forming a second pad within said second IC device layer isolated from said second substrate by said fifth dielectric layer;

depositing a sixth dielectric layer on a second surface of said second substrate;

etching a second region through said second substrate;

depositing a seventh dielectric layer on said sixth dielectric layer and on inner surfaces of said second region for isolation;

selectively removing portions of said fifth, sixth and seventh dielectric layers to expose said second pad;

depositing a second conductive layer through said second region and contacting said second pad to form a second through-substrate via;

selectively removing said second conductive layer from said second surface of said second substrate to provide electrical isolation for said second through-substrate via;

depositing an eighth dielectric layer on said sixth dielectric layer;

forming a second bump making contact to said second through-substrate via; and

joining said first and second bumps of said first and second substrates to provide electrical connectivity between said first and second IC device layers.