Semiconductor device having low floating inductance

• US 5,424,579 A
• Filed: 07/02/1993
• Issued: 06/13/1995
• Est. Priority Date: 07/21/1992
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arai, Kiyoshi, Takagi, Yoshio
• Primary Examiner(s): Ngo, Ngan V.
• Assistant Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/084,957
• Time in Patent Office: 711 Days
• Field of Search: 257/691, 257/692, 257/693, 257/698, 257/690, 257/699, 257/701, 257/678, 257/734, 257/689, 257/696
• US Class Current: 257/690
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A first composite substrate including an insulating substrate, a copper pattern, and a copper layer on opposite surfaces is mounted on a metal base plate. A second composite substrate and semiconductor chips are mounted on the first composite substrate and interconnected by wire bonding. The paths of current flowing in the wires and in a copper pattern of the second composite substrate are antiparallel to the paths of current flowing in respective corresponding portions of the first composite substrate. A semiconductor device is produced in which an increasing switching frequency does not increase a surge voltage generated in ON and OFF switching operations.

Claims

1. A semiconductor device for controlling an input current flowing to a semiconductor chip to provide an output current comprising:

(a) a metal base plate having a major surface;

(b) a first insulating substrate disposed on said major surface of said metal base plate;

(c) a first conductive layer disposed on said first insulating substrate and having a first portion for conducting one of an input current and an output current in a first direction parallel to said major surface;

(d) a second insulating substrate disposed on part of said first conductive layer;

(e) a second conductive layer disposed on said second insulating substrate and having a second portion for conducting the other of the input an output currents in a second direction antiparallel to said first direction, said second portion overlying said first portion; and

(f) a semiconductor chip disposed on one of said first and second conductive layers and electrically connected to said first and second conductive layers.

2. The semiconductor device of claim 1, further comprising:

(g) a first electrode electrically connected to an end of said first conductive layer; and

(h) a second electrode electrically connected to an end of said second conductive layer located on the same side said of said second insulating substrate as said end of said first conductive layer.

3. The semiconductor device of claim 2, further comprising:

(i) a third conductive layer provided between said metal base plate and said first insulating substrate.

4. The semiconductor device of claim 3, wherein

said semiconductor chip includes:

(f-1) a power semiconductor element provided on said first conductive layer; and

(f-2) a flywheel diode provided on said first conductive layer and connected in reverse polarity to said power semiconductor element.

5. The semiconductor device of claim 4, wherein

the respective thickness of said first and second conductive layers is 0.1 to 0.5 mm.

6. The semiconductor device of claim 5, wherein

a spacing between said first and second conductive layers is 0.5 to 1.5 mm.

7. The semiconductor device of claim 6, wherein

said first and second conductive layers are substantially copper.

8. A semiconductor device for controlling an input current flowing to a semiconductor chip to provide an output current comprising:

(a) a metal base plate having a major surface;

(b) a first insulating substrate disposed on said major surface of said metal base plate;

(c) a first conductive layer provided on said first insulating substrate and having a first region for conducting one of an input current and an output current in a first direction parallel to said major surface, and a second peninsular region continuous with said first region and protruding in a second direction different from said first direction on said major surface;

(d) a second insulating substrate provided on said first region;

(e) a second conductive layer provided on said second insulating substrate and having a portion for conducting the other of the input and output in a third direction antiparallel to said first direction, said portion overlying said first region of said first conductive layer; and

(f) at least one semiconductor chip provided on said second region and electrically connected to said first and second conductive layers.

9. The semiconductor device of claim 8, wherein

said at least one semiconductor chip includes

(f-1) a plurality of semiconductor chips spaced in said first direction, and a slit substantially parallel to said second direction in a portion in said second region.

10. The method of claim 9, further comprising the steps of:

(g) a first electrode electrically connected to an end of said first region; and

(h) a second electrode electrically connected to an end of said second conductive layer located on the same side of said second insulating substrate as said end of said first region.

11. The semiconductor device of claim 10, further comprising:

(i) a third conductive layer provided between said metal base plate and said first insulating substrate.

12. The semiconductor device of claim 11, wherein

the respective thickness of said first and second conductive layers is 0.1 to 0.5 mm.

13. The semiconductor device of claim 12, wherein

a spacing between said first and second conductive layers is 0.5 to 1.5 mm.

14. The semiconductor device of claim 13, wherein

said first and second conductive layers are substantially copper.

15. A semiconductor device for controlling an input current flowing to a semiconductor chip to provide an output current, comprising:

(a) a metal base plate having a major surface;

(b) an insulating substrate disposed on said major surface of said metal base plate;

(c) a conductive layer provided on said insulating substrate for conducting on of an input current and output current in a first direction parallel to said major surface;

(d) a semiconductor chip disposed on said conductive layer; and

(e) a wire electrically connected to an upper surface of said semiconductor chip and extending above said conductive layer in a second direction antiparallel to said first direction for conducting the other of the input and output currents.

16. The semiconductor device of claim 15, wherein

said insulating substrate is a first insulating substrate,

said conductive layer is a first conductive layer, and

said semiconductor chip is a first semiconductor chip,

said semiconductor device further comprising:

(f) a second conductive layer selectively formed on said first conductive layer; and

(g) a second semiconductor chip disposed on said second conductive layer, said wire including;

(e-1) a first end electrically connected to said upper surface of said first semiconductor chip; and

(e-2) a second end electrically connected to an upper surface of said second semiconductor chip.

17. The semiconductor device of claim 16,

wherein said first conductive layer includes:

(c-1) a first region on which said first semiconductor chip is placed; and

(c-2) a second peninsular region continuous with said first region and protruding in a second direction substantially perpendicular to said first direction on said major surface,

wherein said second conductive layer is formed on said second region, and

wherein the direction of a current flowing in said second conductive layer is antiparallel to that of a current flowing in said first region.

18. The semiconductor device of claim 17, wherein

said first semiconductor chip includes:

(d-1) a plurality of first semiconductor chips spaced substantially in said first direction on said first region, and

a slit substantially parallel to said first direction in a portion in said first conductive layer.

19. The semiconductor device of claim 18, further comprising:

(h) a first electrode connected electrically to an end of said first conductive layer; and

(i) a second electrode connected electrically to an end of said second conductive layer located on the same side of said end of said first conductive layer.

20. The semiconductor device of claim 18, wherein

the respective thickness of said first and second conductive layers is 0.1 to 0.5 mm.

21. The semiconductor device of claim 20, wherein

a spacing between said first and second conductive layers is 0.5 to 1.5 mm.

22. The semiconductor device of claim 21, wherein

said first and second conductive layers are substantially copper.