Delay time control circuit

• US 5,424,590 A
• Filed: 06/23/1993
• Issued: 06/13/1995
• Est. Priority Date: 06/25/1992
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Inventors: Sato, Kenichi, Aoki, Kouju, Mizuno, Moriaki
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): NGUYEN, TIEP HUU
• Application Number:
  US08/079,799
• Time in Patent Office: 720 Days
• Field of Search: 307/303, 307/597, 307/600, 307/602, 307/603
• US Class Current: 327/273
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

An input signal is provided at first input terminals of a plurality of parallel AND gates in a delay time control circuit. A digital signal from a decoder having a plurality of bits is coupled to second input terminals of the AND gates with one bit coupled per AND gate. The decoder outputs a signal having an a high level in response to an external input control signal. Output signals from the AND gates are coupled to inputs of a plurality of serially connected OR gates.

Claims

1. A delay time control circuit comprising:

a plurality of AND gates having first and second input terminals, respectively, with the first input terminals thereof receiving an input signal to be delayed;

a decoder outputting a digital signal having a plurality of bits, coupled to the second input terminals of the AND gates, said decoder outputting a high level signal in any one bit of the digital signal in response to an external input control signal; and

a plurality of OR gates connected in series, with each of said OR gates receiving an output signal from a respective one of said AND gates.

2. The delay time control circuit according to claim 1, wherein the OR gates are provided in a row on a semiconductor substrate.

3. The delay time control circuit according to claim 1, wherein the AND gates are provided in a row on a semiconductor substrate.

4. The delay time control circuit according to claim 1, wherein the OR gates and AND gates are provided in rows, one of the OR gates and one of the AND gates that are to be mutually connected are adjacently disposed.

5. The delay time control circuit according to claim 1, wherein said plurality of OR gates and AND gates are provided in rows, and one of said plurality of OR gates and one of said plurality of AND gates that are to be mutually connected are adjacently disposed on a semiconductor substrate.

6. A delay time control circuit comprising:

a plurality of AND gates having first and second input terminals, respectively, with the first input terminals thereof receiving an input signal to be delayed;

a decoder outputting a digital signal having a plurality of bits, coupled to the second input terminals of the AND gates, said decoder outputting a high level signal in any one bit of the digital signal in response to an external input control signal; and

a plurality of OR gates connected in series, with each of said OR gates receiving an output signal from a respective one of said AND gates, wherein;

said OR gates are provided in a row on a semiconductor substrate; and

lengths of conducting lines connecting pairs of adjacently disposed OR gates are equal.

7. A delay time control circuit comprising:

a plurality of AND gates having first and second input terminals, respectively, with the first input terminals thereof receiving an input signal to be delayed;

a decoder outputting a digital signal having a plurality of bits, coupled to the second input terminals of the AND gates, said decoder outputting a high level signal in any one bit of the digital signal in response to an external input control signal; and

a plurality of OR gates connected in series, with each of said OR gates receiving an output signal from a respective one of said AND gates, wherein;

said plurality of OR gates and AND gates are provided in rows;

one of said plurality of OR gates and one of said plurality of AND gates that are to be mutually connected are adjacently disposed; and

lengths of conducting lines connecting the OR gates with the AND gates, respectively, are equal.

8. A delay time control circuit comprising:

a plurality of AND gates provided in a row on a semiconductor substrate and having first and second input terminals, with the first input terminals thereof receiving an input signal to be delayed;

a decoder outputting a digital signal having a plurality of bits, the digital signal being coupled to the second input terminals of said AND gates by every bit thereof, and said decoder outputting a high level signal in any one bit of the digital signal in response to an external input control signal;

a plurality of OR gates connected in series to one another, and disposed in a row on a semiconductor substrate, and each of said OR gates receiving an output signal from a respective one of said AND gates;

first conducting lines being equal in length, for connecting adjacently disposed OR gates, wherein;

said OR gates and said AND gates are mutually connected and adjacently disposed on the semiconductor substrate; and

second conducting lines, being equal in length, connect said OR gates with said AND gates, respectively.

9. A delay time control circuit comprising:

a decoder for outputting a digital signal comprising a plurality of bits, said decoder outputting a high level signal for any of said plurality of bits of the digital signal, in response to an external input control signal;

a plurality of AND gates having first and second input terminals, respectively, the first input terminal receiving an input signal to be delayed, and the second input terminal coupled to said decoder, each respective second input terminal receiving one of said plurality of bits of the digital signal from said decoder, each of said plurality of AND gates outputting an output signal; and

a plurality of OR gates connected in series, with each of said OR gates receiving one of said output signals from a respective one of said AND gates.