Differential amplification circuit wherein a DC level at an output terminal is automatically adjusted and a power amplifier wherein a BTL drive circuit is driven by a half wave

• US 5,424,683 A
• Filed: 03/16/1994
• Issued: 06/13/1995
• Est. Priority Date: 03/29/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Yoshiaki
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US08/210,152
• Time in Patent Office: 454 Days
• Field of Search: 307/494, 307/540, 330/255, 330/259, 330/260, 330/265, 330/267
• US Class Current: 330/255
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/307 in push-pull amplifiers

Abstract

A power amplifier with highly efficient power consumption with fewer switching power supplies. The power amplifier comprises a first differential amplifier having two input terminals and a common terminal, a BTL amplifier consisting of a first SEPP OCL and a second SEPP OCL, a nonlinear adder, an adder, a second differential amplifier, and a switching power supply.

Claims

1. A differential amplification circuit wherein a DC level at an output terminal is automatically adjusted, said circuit comprising:

a first differential amplifier comprising two input terminals, two output terminals, and a common input terminal for determining DC levels of said two output terminals for amplifying an AC signal input as a difference between said two input terminals and outputting to said two output terminals output signals of opposite polarity to each other;

a negative feedback circuit for applying negative feedback of mutually equal size between one of said two input terminals and one of said two output terminals and between the other of said two input terminals and the other of said two output terminals;

a nonlinear adder for substantially adding two output signals generated at said two output terminals and clamping a change in the result of the addition to a predetermined value or less; and

a second differential amplifier for applying a comparison output signal responsive to a difference between an output signal of said nonlinear adder and a reference voltage of a reference power supply to said common input terminal of said first differential amplifier.

2. The differential amplification circuit as claimed in claim 1 wherein said first differential amplifier has a pair of transistors for dividing and flowing a current from one constant current source, the current amount of said pair of transistors changing according to signals from said two input terminals, and is responsive to an input signal from said common input terminal for changing the sum of current amounts supplied to two transistors from said constant current source.

3. The differential amplification circuit as claimed in claim 1 wherein said nonlinear adder includes a pair of resistors connected in series and a pair of diodes connected in series in opposite directions to each other, said pair of resistors and said pair of diodes having one end connected to each of said two output terminals and intermediate points of connection of the resistors and the diodes connected to said second differential amplifier.

4. The differential amplification circuit as claimed in claim 1 wherein two outputs of said first differential amplifier are input to a pair of push-pull output stages and BTL drive of a load is performed by output of said pair of push-pull amplification stages.

5. The differential amplification circuit as claimed in claim 4 wherein each of said pair of push-pull output stages has a pair of transistors of opposite polarity to each other connected in series between power supply and ground and the load is connected between a connection point of said pair of transistors of one push-pull output stage and a connection point of said pair of transistors of the other push-pull output stage.

6. The differential amplification circuit as claimed in claim 5 further including a switching power supply for changing a power supply of said pair of push-pull output stages in response to a signal supplied to said load.

7. The differential amplification circuit as claimed in claim 6 wherein said nonlinear adder adds signals at both ends of said load.

8. The differential amplification circuit as claimed in claim 7 wherein two bias circuits each for adjusting a DC level of an input signal to the push-pull output stage are further disposed between said two output terminals of said first differential amplifier and said pair of push-pull output stages.