Non-conductive end layer for integrated stack of IC chips

• US 5,424,920 A
• Filed: 04/25/1994
• Issued: 06/13/1995
• Est. Priority Date: 05/15/1992
• Status: Expired due to Term

• Current Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Miyake, Michael K.
• Primary Examiner(s): LEDYNH, BOT L
• Application Number:
  US08/232,739
• Time in Patent Office: 414 Days
• Field of Search: 361/728-730, 361/735, 361/744, 361/784-785, 361/792, 361/796, 29/846, 29/852, 29/592.1, 29/845, 437/51, 437/208, 437/205, 437/915, 257/685-686, 257/704, 257/777
• US Class Current: 361/735
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.

Claims

1. An integrated stack of layers which form a three-dimensional structure having an access plane, and containing embedded integrated circuitry (IC), comprising:

a plurality of layers which are IC chips, each IC chip having an edge forming part of the access plane, on which a multiplicity of electrical leads are accessible;

a cap layer at one end of the stack, which constitutes an insulating layer, and which has (a) a plurality of holes extending between its inner surface and its outer surface, and (b) a plurality of terminals at the access plane;

a plurality of traces next to the inner surface of the cap layer, each leading from one or more of the holes to one or more of the access plane terminals;

a plurality of cap layer terminals on the outer surface of the cap layer each leading to one or more of the holes;

conducting material extending through each hole to electrically connect the desired trace to the desired cap layer terminal; and

conducting material on the access plane connecting each access plane terminal of the cap layer to one or more leads on one or more IC chips.

2. The integrated stack of layers of claim 1, in which the cap layer has a coefficient of thermal expansion similar to the coefficient of thermal expansion of the material which forms the IC chip layers.

3. The integrated stack of layers of claim 2, in which the material forming the IC chip layers is silicon, and the material forming the cap layer is aluminum nitride.

4. The integrated stack of layers of claim 1, which also comprises:

a second insulating layer, which is located at the other end of the stack from the cap layer, so that both ends of the stack are covered by insulating layers.

5. The integrated stack of layers of claim 1, in which:

continuous metalization is provided by each trace, the conducting material extending through each hole to said trace, and the terminal connected to said hole; and

such continuous metalization is formed on the cap layer prior to its inclusion in the stack.

6. The integrated stack of layers of claim 1, in which the conducting material in each hole in the cap layer fills the hole.

7. The integrated stack of layers of claim 1, in which:

each terminal is located adjacent to a separate hole in the cap layer.

8. The integrated stack of layers of claim 1, in which:

each terminal is connected to a separate hole by a separate conductor.

9. The integrated stack of layers of claim 1 in which the area of the cap layer fits into the same area as the stack of IC chips.

10. The integrated stack of layers of claim 1 in which the IC chips in the stack are secured in planar engagement with one another.

11. The integrated stack of layers of claim 10 in which the cap layer is secured in planar engagement with the stack of IC chips.

12. An integrated stack of layers which form a three dimensional structure having an access plane, and containing embedded integrated circuitry (IC), comprising:

a plurality of layers which are IC chips, each IC Chip extending to the access plane, and each having a multiplicity of electrical leads at the access plane;

a cap layer at one end of the stack, which constitutes an insulating layer and which is not an IC chip;

terminals on the outer surface of the cap layer which are adapted to be connected to external circuitry;

conductors on the access plane which form T-connects with the electrical leads on the IC chip layers; and

flat metallic conductors on the cap layer which contact the conductors on the access plane and which lead to the respective terminals on the outer surface of the cap layer.

13. The integrated stack of layers of claim 12, in which:

the cap layer has a plurality of holes extending from its inner surface to its outer surface; and

the conductors on the cap layer comprise (a) traces next to the inner surface of the cap layer, each of which leads from one of the holes to a conductor on the access plane of the stack; and

(b) conductors which extend through the holes in the cap layer, each connecting to one of the traces.

14. The integrated stack of layers of claim 13, in which:

the terminals are located in groups near edges of the cap layer; and

separate conductors on the outer surface of the cap layer lead from separate holes to separate terminals.

15. The integrated stack of layers of claim 12 in which the area of the cap layer fits into the same area as the stack of IC chips.

16. The integrated stack of layers of claim 12 in which the IC chips in the stack are secured in planar engagement with one another.

17. The integrated stack of layers of claim 16 in which the cap layer is secured in planar engagement with the stack of IC chips.

18. The method of fabricating an electronic package which comprises:

stacking and securing together a plurality of IC chips, each chip having embedded IC circuitry and each having leads which extend to the chip edge, the lead-carrying edges of the chips constituting a stack access plane;

forming an insulated end layer having a flat inner surface and a flat outer surface;

forming holes extending through the end layer;

forming conductors next to the inner surface of the end layer, each of which is adapted to connect a hole to the access plane of the stack;

forming terminals on the outer surface of the end layer, each of which terminals is connected to a hole;

forming conductors which extend through the holes in the end layer, in order to provide continuous electrical conduction from each terminal to the access plane of the stack;

combining the end layer with the plurality of IC chips; and

forming an integrated stack which includes the end layer.

19. The method of claim 18, in which:

the conductors fill the holes in the end layer, in order to prevent flow of material through the holes.

20. The method of claim 18, in which:

the terminals on the outer surface of the end layer are formed near edges of the end layer; and

conductors are formed on the outer surface of the end layer connecting the terminals to the holes.