Method and apparatus for debugging reconfigurable emulation systems

• US 5,425,036 A
• Filed: 09/18/1992
• Issued: 06/13/1995
• Est. Priority Date: 09/18/1992
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Liu, Dick L., Choi, Kenneth S. K., Li, Jeong-Tyng, Huang, Thomas B.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Shah, Kamini S.
• Application Number:
  US07/947,308
• Time in Patent Office: 998 Days
• Field of Search: 371/23, 371/22.2, 371/22.1, 371/22.3, 364/488, 364/489, 364/578, 364/DIG. 1, 364/DIG. 2, 364/232.2, 364/927.81, 364/579, 364/580, 364/16.2
• US Class Current: 714/735
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Claims

1. A method for testing a reconfigurable emulation system to ensure that it accurately implements a netlist description of a functional circuit, the method comprising the steps of:

configuring the reconfigurable emulation system to implement the functional circuit;

applying stimuli to the functional circuit implemented in the reconfigurable emulation system, thereby causing the functional circuit implemented in the reconfigurable emulation system to generate an actual response, said stimuli applied in a first emulation cycle;

detecting when said actual response differs from an expected response during said first emulation cycle;

if the actual response differs from the expected response, specifying a particular net where an apparent error is located in the netlist description and the time within said first emulation cycle when said apparent error occurred; and

modifying said stimuli applied to the functional circuit implemented in the reconfigurable emulation system to include a read-back signal which, during a subsequent emulation cycle, is applied to said particular net where said apparent error is located at a time corresponding to said time of said apparent error, said read-back signal causing the reconfigurable emulation system to output state information of the reconfigurable emulation system at said particular net where said apparent error is located at said time of said apparent error.

2. The method of claim 1 further comprising the step of examining said state information to determine whether said apparent error was caused by an improper implementation of the netlist description in the reconfigurable emulation system or by an error in the netlist description.

3. The method of claim 2 wherein if said apparent error was caused by an error in the netlist description, the method further comprises the step of correcting the netlist description to eliminate said apparent error.

4. The method of claim 1 wherein the reconfigurable emulation system includes at least one field programmable gate array, wherein said at least one FPGA can be triggered to read back the state of flip-flops and latches employed therein.

5. The method of claim 1 wherein the stimuli comprises data and clock signals.

6. The method of claim 1 wherein the stimuli comprises a plurality of digital input vector signals including both data and clock signals.

7. The method of claim 1 wherein the state information comprise latch and flip-flop states internal to the reconfigurable emulation system which are shifted-out serially from the reconfigurable emulation system to at least one external port coupled thereto.

8. The method of claim 1 wherein the modified stimulus a modified clock signal.

9. The method of claim 2 further comprising reconfiguring the reconfigurable emulation system to implement said corrected netlist description.

10. A method for functionally testing a circuit undergoing logic emulation comprising the steps of:

configuring a plurality of reprogrammable logic devices with a netlist description of an integrated circuit;

applying digital input vectors to said configured reprogrammable logic devices to cause said configured reprogrammable logic devices to generate digital output signals;

comparing said digital output vectors with said digital output signals to determine a difference between said digital output vectors and said digital output signals;

if said difference is detected, modifying said digital input vectors to include read-back trigger point information within the digital input vectors, said read-back trigger point information comprising a particular net within the netlist description and a time at which said difference occurred;

applying the modified digital input vectors to the configured reprogrammable logic devices to cause the configured reprogrammable logic devices to generate modified digital output signals, said modified digital output signals including state information from registers where said particular net is implemented within said reprogrammable logic devices at said time at which said difference occurred;

examining said state information to determine whether said difference was caused by an error in said netlist; and

if said difference was caused by an error in said netlist, correcting said netlist so that said difference will not occur.

11. A method of debugging a prototype integrated circuit design prior to fabricating the prototype integrated circuit design comprising:

mapping a netlist description of the integrated circuit design into a reconfigurable emulation system, thereby creating an emulated integrated circuit;

operating said emulated integrated circuit in a target system by running actual input stimuli through said target system, said target system comprising a system where the fabricated version of the prototype integrated circuit design will reside, thereby running the prototype integrated circuit under real-time operating conditions;

if said target system fails during said operating step, specifying a particular net within the netlist description where an apparent error is located and a point in time during said operating step where said apparent error took place;

modifying said input stimuli applied to said target system such that said modified input stimuli will induce said reconfigurable emulation system to capture state information of memory elements within said reconfigurable emulation system where said particular net is mapped at said point in time where said apparent error took place;

re-operating said emulated integrated circuit with said modified input stimuli;

examining said state information to determine how to correct the netlist description to eliminate said apparent error; and

correcting the netlist description to eliminate said apparent error.