Method DRAM polycide rowline formation

• US 5,425,392 A
• Filed: 05/26/1993
• Issued: 06/20/1995
• Est. Priority Date: 05/26/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Gonzalez, Fernando, Thakur, Randhir P. S., Martin, Annette L.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/067,660
• Time in Patent Office: 755 Days
• Field of Search: 437/52, 437/60, 437/200, 437/173, 437/174, 437/233, 437/235, 437/238, 437/248, 437/40, 148/DIG. 91
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation

Abstract

The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500° C. to 1250° C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi_x) and titanium silicide (TiSi_x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF₆, TMAT and TiCl₄.

Claims

1. A method for reducing sheet resistance of a conductive rowline feature, comprising the steps of:

providing a silicon substrate having a gate oxide layer superjacent within a chamber;

forming a polysilicon layer superjacent said gate oxide layer in situ by exposing said silicon substrate to a first gas and radiant energy, said energy generating a temperature within the range of 500°

C. to 1250°

C. for at least 10 seconds by rapid thermal processing, said first gas comprising at least one of silane, disilane, and dichlorosilane;

doping said polysilicon substrate with phosphorus by exposing said silicon substrate to radiant energy and a second gas, said energy generating a temperature substantially within the range of 500°

C. to 1250°

C. for at least 10 seconds by rapid thermal processing; and

forming a conductive layer superjacent said polysilicon by exposing said silicon substrate to radiant energy and a third gas, said conductive layer comprising at least one of tungsten silicide and titanium silicide, said energy generating a temperature substantially within the range of 500°

C. to 1250°

C. for at least 10 seconds by rapid thermal processing, said third gas comprising at least one of WF₆, TMAT and TiCl₄.