Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

• US 5,426,072 A
• Filed: 01/21/1993
• Issued: 06/20/1995
• Est. Priority Date: 01/21/1993
• Status: Expired due to Term

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Finnila, Ronald M.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/006,601
• Time in Patent Office: 880 Days
• Field of Search: 437/208, 437/915, 437/974, 257/686, 257/700, 257/777
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Claims

1. A method for fabricating a circuit assembly, comprising the steps of:

(a) providing a multilayered wafer having a first substrate, an electrically insulating dielectric oxide layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric oxide layer;

(b) processing the semiconductor material layer to form at least one electrically conductive feedthrough through the semiconductor material layer and to form circuitry within the semiconductor material layer;

(c) forming interconnection means that overlie the semiconductor material layer and that are electrically coupled to the at least one feedthrough;

(d) attaching a temporary substrate such that the interconnection means are interposed between the semiconductor material layer and the temporary substrate;

(e) removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric oxide layer; and

(f) forming further interconnection means through the exposed dielectric oxide layer for electrically coupling at least to the at least one feedthrough, thereby fabricating a first circuit assembly.

2. The method of claim 1 wherein the step of attaching includes a step of providing a protective material at a periphery of the multilayered wafer, the protective material protecting edges of the layer of semiconductor material during the step of etching.

3. The method of claim 1 wherein the first substrate is comprised of silicon, and wherein the step of etching employs a KOH solution.

4. The method of claim 1 wherein the step of etching employs plasma etching.

5. The method of claim 1 wherein the step of forming interconnection means includes an initial step of depositing an electrically insulating overglass layer on the semiconductor material layer.

6. The method of claim 1 wherein the step of removing the first substrate comprises the steps of first lapping and then etching the first substrate.

7. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming an indium bump in registration with said at least one feedthrough, the indium bump being electrically coupled to said at least one feedthrough.

8. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming at least one indium bump, the at least one indium bump being electrically coupled to said at least one feedthrough.

9. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming at least one solder bump, the at least one solder bump being electrically coupled to said at least one feedthrough.

10. The method of claim 1 and further comprising a step of sawing the first circuit assembly into a plurality of smaller circuit assemblies, each of said smaller circuit assemblies including a portion of the temporary substrate, at least one interconnection means, and at least one further interconnection means.

11. The method of claim 10 and further comprising the steps of:

removing the portion of the temporary substrate from a first smaller circuit assembly;

stacking a second smaller circuit assembly upon the first smaller circuit assembly;

electrically interconnecting the further interconnection means of the second smaller circuit assembly to the interconnection means of the first smaller circuit assembly; and

removing the portion of the temporary substrate from the second smaller circuit assembly.

12. The method of claim 1 and further comprising the steps of:

removing the temporary substrate from the first circuit assembly;

stacking a second circuit assembly upon the first circuit assembly, the second circuit assembly being fabricated in accordance with the steps (a) through (f);

electrically interconnecting the further interconnection means of the second circuit assembly to the interconnection means of the first circuit assembly; and

removing the temporary substrate from the second circuit assembly.

13. The method of claim 12 and further comprising the step of sawing the electrically interconnected first and second circuit assemblies into a plurality of smaller, electrically interconnected circuit assemblies.

14. A method for fabricating a three-dimensional integrated circuit assembly, comprising the steps of:

(a) providing a first multilayered wafer having a first substrate, an electrically insulating dielectric oxide layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric oxide layer;

(b) processing the semiconductor material layer to form at least one electrically conductive feedthrough through the semiconductor material layer and to form circuitry as required within the semiconductor material layer;

(c) forming interconnection means that overlies the semiconductor material layer and that is electrically coupled to the at least one feedthrough;

(d) attaching the first wafer to a temporary substrate such that the interconnection means is interposed between the semiconductor material layer and the temporary substrate;

(e) removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric oxide layer;

(f) forming further interconnection means through the exposed dielectric oxide layer for electrically contacting at least the at least one feedthrough, the step of forming further interconnection means resulting in a first circuit assembly that includes the processed semiconductor material layer, the interconnection means formed over a first major surface of the processed semiconductor material layer, and the further interconnection means formed over a second major surface of the processed semiconductor layer;

(g) coupling the further interconnection means to interconnection means of a second multilayered wafer, the second multilayered wafer including a supporting substrate disposed on a surface opposite to a surface that underlies the interconnection means of the second multilayered wafer; and

(h) removing the temporary substrate from the first circuit assembly.

15. The method of claim 14 wherein the first substrate is comprised of silicon, and wherein the step of etching employs a KOH solution.

16. The method of claim 14 wherein the step of etching includes a step of plasma etching.

17. The method of claim 14 and further comprising the steps of:

(i) coupling the further interconnection means of a second circuit assembly to the interconnection means of the first circuit assembly, thereby forming a stack of circuit assemblies, the second circuit assembly being fabricated in accordance with steps (a) through (f); and

(j) removing a temporary substrate from the second circuit assembly.

18. The method of claim 17 and, after repeating steps (i) and (j) until a last circuit assembly is coupled to the stack of circuit assemblies, further comprising a step of coupling the interconnection means of the last circuit assembly to interconnection means disposed over a major surface of a further substrate, the major surface of the further substrate having a surface area that is greater than a surface area of the first major surface of an individual one of circuit assemblies of the stack of circuit assemblies, the further substrate being provided with electrical contact means for coupling the stack of circuit assemblies to other circuitry.

19. The method of claim 17 and, after repeating steps (i) and (j) until a last circuit assembly is coupled to the stack of circuit assemblies, the last circuit assembly includes electrical contact means for coupling the stack of circuit assemblies to other circuitry.

20. The method of claim 14 wherein the step of forming interconnection means includes an initial step of depositing an electrically insulating overglass layer on the semiconductor material layer.

21. The method of claim 14 wherein the step of removing the first substrate comprises the steps of first lapping and then etching the first substrate.

22. The method of claim 14 wherein steps of forming interconnection means and further interconnection means each include a step of forming an indium bump that is electrically coupled to the at least one feedthrough.

23. The method of claim 14 wherein steps of forming interconnection means and further interconnection means each include a step of forming a solder bump that is electrically coupled to the at least one feedthrough.

24. The method of claim 17 and, after repeating steps (i) and (j) until a last circuit assembly is coupled to the stack of circuit assemblies, further comprising a step of sawing the stack of circuit assemblies into a plurality of stacks of circuit assemblies.