Thin-film transistor having an inlaid thin-film channel region

• US 5,426,315 A
• Filed: 10/04/1993
• Issued: 06/20/1995
• Est. Priority Date: 10/04/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pfiester, James R.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/131,190
• Time in Patent Office: 624 Days
• Field of Search: 257/66, 257/67, 257/69, 257/74, 257/347, 257/350, 257/351, 257/369, 257/900, 257/903, 257/904, 257/411
• US Class Current: 257/66
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

Claims

1. A thin-film transistor comprising:

a multi-layered insulating structure overlying a substrate and having a substantially vertical side, wherein the multi-layered insulating structure includes a channel spacing layer;

a recess in the substantially vertical side, wherein the channel spacing layer is withdrawn from the vertical side and forms an inner wall of the recess;

a thin-film channel region residing substantially within the recess;

thin-film source and drain regions electrically connected to the thin-film channel region; and

a gate electrode intermediate to the source and drain regions and separated from the thin-film channel region by a gate dielectric layer.

2. The device of claim 1, wherein the thin-film source and drain regions are each comprised of a semiconductor layer, and wherein the thin-film drain region overlies a first portion of the vertical side and the thin-film source region overlies a second portion of the vertical side.

3. A thin-film transistor comprising:

a multi-layered insulating structure overlying a substrate and having a substantially vertical side,

wherein the multi-layered insulating structure includes,

a first insulating layer,

a second insulating layer, and

a third insulating layer intermediate to the first and second insulating layers,

wherein the third insulating layer is withdrawn from the side of the multi-layered insulating structure;

a recess in the substantially vertical side,

wherein a portion of the third insulating layer forms an inner wall of the recess;

a thin-film channel region residing substantially within the recess;

thin-film source and drain regions electrically connected to the thin-film channel region; and

a gate electrode intermediate to the source and drain regions and separated from the thin-film channel region by a gate dielectric layer.

4. A thin-film transistor comprising:

a multi-layered insulating structure overlying a substrate and having a substantially vertical side;

a recess in the substantially vertical side;

a thin-film channel region residing substantially within the recess;

thin-film source and drain regions electrically connected to the thin-film channel region,

wherein the thin-film drain region resides in the recess and is comprised of a semiconductor layer, and wherein the thin-film source region overlies a portion of the vertical side; and

a gate electrode intermediate to the source and drain regions and separated from the thin-film channel region by a gate dielectric layer.

5. A thin-film transistor electrically coupled to bulk transistor comprising:

a semiconductor substrate having a gate dielectric layer thereon;

an opening in the gate dielectric layer exposing a contact region in the substrate;

a driver gate electrode overlying the gate dielectric layer and overlying a first portion of the contact region;

a multi-layered insulating structure overlying the driver gate electrode, the multi-layered insulating structure having a substantially vertical side;

a recess in the substantially vertical side;

a thin-film channel region residing within the recess;

a thin-film drain region overlying a portion of the vertical side and electrically contacting the thin-film channel region; and

a thin-film gate electrode overlying a portion of the multi-layered insulating structure and electrically coupling the thin-film drain region to a second portion of the contact region.

6. The device of claim 5, wherein the multi-layered insulating structure further comprises:

a first insulating layer;

a second insulating layer; and

a third insulating layer intermediate to the first and second insulating layers,

wherein the third insulating layer is withdrawn from the side of the multi-layered structure, and

wherein a portion of the third insulating layer forms an inner wall of the recess.

7. The device of claim 5, wherein the thin-film channel region is polycrystalline silicon and the source and drain regions are silicon germanium.

8. A thin-film transistor comprising:

a shared-gate electrode;

a multi-layered insulating structure overlying the shared-gate electrode, wherein the multi-layered insulating structure has a substantially vertical side, and wherein the multi-layered insulating structure includes a channel spacing layer;

a recess in the substantially vertical side, wherein the channel spacing layer is withdrawn from the vertical side and forms an inner wall of the recess;

thin-film source and drain regions overlying first and second portions of the vertical side, respectively; and

a thin-film channel region residing within the recess and electrically connected to the thin-film source and drain regions, wherein the electrical conduction within the thin-film channel region is controlled by the shared-gate electrode.

9. The device of claim 8, wherein the thin-film drain region is silicon germanium and the thin-film channel region is polycrystalline silicon.

10. The device of claim 8, wherein the thin-film drain region is polycrystalline silicon and the thin-film channel region is silicon germanium.

11. The device of claim 8 further comprising:

a second gate electrode overlying the multi-layered insulating structure and electrically coupled to the shared-gate electrode by an electrically conductive layer residing in a portion of the recess.

12. A thin-film transistor comprising:

a shared-gate electrode;

a multi-layered insulating structure overlying the gate electrode, wherein the multi-layered insulating structure has a substantially vertical side,

wherein the multi-layered insulating structure further includes, a gate dielectric layer overlying the shared-gate electrode, a first insulating layer, and a second insulating layer intermediate to the first insulating layer and the gate dielectric layer,

wherein the second insulating layer is withdrawn from the side of the multi-layered body, and

wherein a portion of the second insulating layer forms an inner wall of the recess

a recess in the substantially vertical side;

thin-film source and drain regions overlying first and second portions of the vertical side, respectively; and

a thin-film channel region residing within the recess and electrically connected to the thin-film source and drain regions, wherein the electrical conduction within the thin-film channel region is controlled by the shared-gate electrode.

13. A thin-film transistor comprising:

a shared-gate electrode;

a multi-layered insulating structure overlying the gate electrode, wherein the multi-layered insulating structure has a substantially vertical side;

a recess in the substantially vertical side;

thin-film source and drain regions overlying first and second portions of the vertical side, respectively; and

a thin-film channel region residing within the recess and electrically connected to the thin-film source and drain regions,

wherein the thin-film drain region includes a lightly-doped region adjacent to the thin-film channel region, and heavily doped regions on either side of the lightly-doped region, and

wherein the electrical conduction within the thin-film channel region is controlled by the shared-gate electrode.

14. A thin-film transistor comprising:

a shared-gate electrode;

a multi-layered insulating structure overlying the gate electrode, wherein the multi-layered insulating structure has a substantially vertical side;

a recess in the substantially vertical side;

thin-film source and drain regions overlying first and second portions of the vertical side, respectively; and

a thin-film channel region residing within the recess and electrically connected to the thin-film source and drain regions,

wherein the thin-film channel region extends outward from the recess and overlies a third portion of the vertical side, and

wherein the electrical conduction within the thin-film channel region is controlled by the shared-gate electrode.

15. A thin-film transistor electrically coupled to substrate transistor comprising:

a semiconductor substrate having a gate dielectric layer thereon;

an opening in the gate dielectric layer exposing a contact region in the substrate;

a driver gate electrode overlying the gate dielectric layer;

a multi-layered insulating structure overlying the driver gate electrode, wherein a portion of the driver gate electrode is exposed by the multi-layered insulating structure;

a thin-film channel region residing within a recess in the multi-layered insulating structure;

a thin-film drain region integral with the thin-film channel region; and

a thin-film gate electrode overlying the contact region, the thin-film drain region, the exposed portion of the first gate electrode and extending beneath the thin-film drain region and a portion of the first gate electrode, wherein the thin-film gate electrode electrically couples the thin-film drain region and the driver gate electrode to the contact region.

16. A thin-film transistor electrically coupled to a substrate transistor within a memory cell comprising:

a substrate having first and second active regions therein;

a shared-gate electrode overlying the first active region and electrically contacting the second active region;

a multi-layered insulating structure overlying the shared-gate electrode, wherein the multi-layered insulating structure has a substantially vertical side;

a recess in the substantially vertical side;

a thin-film channel region residing within the recess; and

a thin-film drain region overlying a first portion of the multi-layered insulating structure and electrically coupling a first portion of the thin-film channel region to the first active region.

17. The thin-film transistor of claim 16 further comprising a Vcc interconnect layer overlying a second portion multi-layered insulating structure and electrically coupled to a second portion of the thin-film channel region, wherein a portion of the Vcc interconnect layer functions as a thin-film source region of the thin-film transistor.