Local bus - I/O Bus Computer Architecture

• US 5,426,739 A
• Filed: 10/14/1992
• Issued: 06/20/1995
• Est. Priority Date: 03/16/1992
• Status: Expired due to Term

• Current Assignee: OPTi Incorporated
• Original Assignee: OPTi Incorporated
• Inventors: Lin, Fong Lu, Ghosh, Subir K., Chen, Win, Shaw, Jhyping, Chen, Chen-Yung V.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US07/961,773
• Time in Patent Office: 979 Days
• Field of Search: 395/325, 395/275, 395/250, 395/500, 439/60
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

In a computer system, one or more ISA connector sockets is replaced by a connector structure which carries both ISA signals and local bus signals. The connector structure is arranged such that a standard ISA accessory card may be inserted, in which case only ISA signals are coupled to or from the card. "Local bus" accessory cards may also be designed for insertion into such a connector, and these cards may connect to one or more signal lines of the local bus either additionally or instead of connections made to the ISA bus. By physical or other means, ISA accessory cards are prevented from unintentional contact with connector contacts which are coupled to local bus signal lines. The connector structure may advantageously comprise an EISA-type connector socket.

Claims

1. Computer apparatus, for use with accessory cards of selectably a first or second type, said accessory cards each having connection pads, comprising:

a circuit board;

an I/O bus having I/O bus signal lines including I/O bus data lines, at least part of each of said I/O bus signal lines being supported by said circuit board;

a local bus having local bus signal lines including local bus data lines, at least part of each of said local bus signal lines being supported by said circuit board;

a source of local bus cycles coupled to said local bus;

interface circuitry connected to said local bus and said I/O bus which transmits data between said local bus data lines and said I/O bus data lines in response to only selected ones of said local bus cycles; and

an edge card socket having a slot for accepting a single accessory card, said socket being supported by said circuit board and having first and second distinct pluralities of contacts, at least one of said first plurality of contacts being coupled to a corresponding first one of said I/O bus signal lines on said circuit board and at least one of said second plurality of contacts being coupled to a corresponding second one of said local bus signal lines on said circuit board, said first and second pluralities of contacts in said edge card socket being arranged such that connection pads on accessory cards of said first type electrically contact contacts in said first plurality of contacts, including said contact coupled to the first I/O bus signal line, when accepted by said edge card socket, no connection pads on accessory cards of said first type electrically contacting contacts in said second plurality of contacts, including said contact coupled to the second local bus signal line, when accepted by said edge card socket, and such that connection pads on accessory cards of said second type electrically contact contacts in said second plurality of contacts, including said contact coupled to the second local bus signal line, when accepted by said edge card socket.

2. Computer apparatus according to claim 1, wherein all of said local bus data lines are coupled to corresponding ones of said second plurality of contacts.

3. Computer apparatus according to claim 2, wherein all of said I/O bus data lines are coupled to corresponding ones of said first plurality of contacts.

4. Computer apparatus according to claim 1, wherein said accessory cards of said first type include accessory cards of first and second sub-types, accessory cards of said first sub-type having connection pads for exactly eight data lines and accessory cards of said second sub-type having connection pads for 16 data lines, and wherein said I/O bus signal lines include 16 I/O bus data lines, all of which are coupled to corresponding ones of said first plurality of contacts, said first plurality of contacts being arranged to couple eight of said 16 I/O bus data lines to respective data lines on accessory cards of said first sub-type when accepted by said edge card socket, and said first plurality of contacts being arranged to couple said 16 I/O bus data lines to respective data lines on accessory cards of said second sub-type when accepted by said edge card socket.

5. Computer apparatus according to claim 1, wherein said edge card socket has a slot for accepting said accessory card, said slot being no longer than the edge card connector of a standard 16-bit ISA accessory card.

6. Computer apparatus according to claim 1, wherein said local bus signal lines include a plurality of local bus control lines coupled to contacts in said edge card socket, wherein all of the local bus control lines in said plurality of local bus control lines are coupled to corresponding ones of said second plurality of contacts.

7. Computer apparatus according to claim 6, wherein said I/O bus signal lines include a plurality of I/O bus control lines, all of which are coupled to corresponding ones of said first plurality of contacts.

8. Computer apparatus according to claim 7, wherein said I/O bus signal lines include additional I/O bus control lines distinct from said plurality of I/O bus control lines, said additional I/O bus control lines not being coupled to any contact on said edge card socket.

9. Computer apparatus according to claim 8, wherein said additional I/O bus control lines include only DMA request and acknowledge lines and interrupt request lines.

10. Computer apparatus according to claim 8, wherein said I/O bus conforms to the ISA standard, and wherein said additional I/O bus control lines consist of the DACK3, DRQ3, DACK0, DRQ0, DACK5, DRQ5, DACK6, DRQ6, IRQ11 and IRQ12 ISA control lines.

11. Computer apparatus according to claim 8, wherein said local bus signal lines include additional local bus signal lines coupled to corresponding ones of said first plurality of contacts and not coupled to any of said second plurality of contacts, and wherein said additional local bus signal lines are coupled to those of said first plurality of contacts which are vacated by said additional I/O bus control lines.

12. Computer apparatus according to claim 8, wherein said local bus signal lines include additional local bus signal lines coupled to corresponding ones of said first plurality of contacts and not coupled to any of said second plurality of contacts, and wherein said additional local bus signal lines include high order local bus address lines.

13. Computer apparatus according to claim 8, wherein said local bus signal lines include additional local bus signal lines coupled to corresponding ones of said first plurality of contacts and not coupled to any of said second plurality of contacts, and wherein said additional local bus signal lines include CA(31:

26), BS8, BS16 and HLDA local bus signal lines.

14. Computer apparatus according to claim 1, wherein said local bus signal lines include additional local bus signal lines coupled to corresponding ones of said first plurality of contacts and not coupled to any of said second plurality of contacts.

15. Computer apparatus according to claim 1, wherein said source of local bus cycles comprises a microprocessor coupled to lines of said local bus and supported by said circuit board.

16. Computer apparatus according to claim 1, wherein said source of local bus cycles comprises:

a modularity connector coupled to said signal lines of said local bus and supported by said circuit board; and

a microprocessor coupled to signal lines of said local bus removably via said modularity connector.

17. Computer apparatus according to claim 1, wherein all of said local bus data lines are connected to corresponding ones of said second plurality of contacts, and wherein said source of local bus cycles comprises:

a microprocessor having data leads connected directly to said local bus data lines.

18. Computer apparatus according to claim 17, wherein said local bus signal lines further include a plurality of local bus control lines, all of which are connected to corresponding ones of said second plurality of contacts, wherein said microprocessor further has control leads connected directly to said plurality of local bus control lines.

19. Computer apparatus according to claim 1, wherein all of said local bus data lines are connected to corresponding ones of said second plurality of contacts, and wherein said source of local bus cycles comprises:

a microprocessor having data leads coupled to said local bus data lines via a bi-directional buffer.

20. Computer apparatus according to claim 1, wherein all of said local bus data lines are connected to corresponding ones of said second plurality of contacts, and wherein said source of local bus cycles comprises:

a microprocessor having data leads coupled to said local bus data lines via a bi-directional latch.

21. Computer apparatus according to claim 1, wherein said local bus signal lines include a plurality of local bus control lines, and wherein said source of local bus cycles comprises:

a microprocessor having a plurality of control leads corresponding to said plurality of local bus control lines; and

means for asserting signals on said plurality of local bus control lines to conduct a cycle over said local bus in response to signals received from said microprocessor control leads, and for indicating termination of said local bus cycle to said microprocessor over said microprocessor control leads in response to completion signals received over said local bus control lines.

22. Computer apparatus according to claim 21, further comprising a cache memory, wherein said means for asserting is further for controlling said cache memory in response signals received over said microprocessor control leads.

23. Computer apparatus according to claim 1, wherein said edge card socket comprises:

a molded box with an elongated opening along its upper surface forming an interior slot;

at least two levels of spring-loaded contacts on at least one interior wall of said slot; and

transverse walls disposed within the interior of said slot.

24. Computer apparatus according to claim 23, wherein said first level of contacts is staggered with respect to said second level of contacts.

25. Computer apparatus according to claim 23, further comprising at least two levels of spring-loaded contacts on opposite walls of said slot.

26. Computer apparatus according to claim 25, wherein said first level of contacts is staggered with respect to the second level of contacts.

27. Computer apparatus according to claim 1, wherein said edge card socket comprises:

a molded box with an elongated opening along its upper surface forming an interior slot;

at least two levels of contacts, being an upper level and a lower level of spring-loaded contacts, on at least one interior wall of said slot; and

transverse walls disposed within the interior of said slot, the height of said transverse walls being lower than said upper level of contacts such that said walls limit the insertion of a mating card edge to permit mating with said upper level of contacts and not said lower level of contacts.

28. Computer apparatus according to claim 1, further comprising a particular accessory card of said second type, said particular accessory card including:

an on-board bus having on-board data lines coupled to connection pads arranged to electrically contact contacts in said second plurality of contacts when accepted by said edge card socket; and

a peripheral device controller on said particular accessory card, said peripheral device controller providing read data on said on-board data lines in response to control signals received by said peripheral device controller via said edge card socket.

29. Computer apparatus according to claim 28, wherein said peripheral device controller receives said control signals via contacts in said first plurality of contacts.

30. Computer apparatus, comprising:

an ISA bus having at least the following industry standard signals;

SD(15;

0), SA(19;

0), LA(23;

17), NOWS#, SMWTC#, SMRDC#, IOW#, IOR#, REFRESH#, BCLK, TC, BALE, OSC, IOCS#, MASTER#, IOCHCK#, CHRDY, AEN#, SBHE#, MRDC#, and MWTC#;

a local bus having local bus signal lines including a plurality of data, address and control lines;

a source of cycles on said local bus;

interface circuitry connected to said local bus and said ISA bus which transmits data between said local bus data lines and said ISA bus SD(15;

0) lines in response to only selected ones of said local bus cycles; and

an edge card connector socket having a slot with two opposing interior walls, an upper pair of rows of contacts opposing each other from said opposing walls, and a lower pair of rows of contacts opposing each other from said opposing walls,

all of said listed ISA bus signal lines being connected to respective contacts in said upper rows of contacts, and all of said contacts in said lower rows of contacts being connected to respective ones of said local bus signal lines.

31. Computer apparatus according to claim 30, wherein said plurality of local bus signal lines connected to said contacts in said lower row of contacts include:

CA(25;

2), CD(31;

0), BE#(3;

0), DRAMS#, HRQ0, M/IO#, W/R#, SCLK, LDEV#, READY#, HLDA1, ADS#, D/C#, and RDYO#.

32. Computer apparatus according to claim 31, wherein said local bus further comprises additional signal lines connected to respective contacts in said upper rows of contacts and not connected to any contacts in any said lower rows of contacts, said additional local bus signal lines including:

CA(31;

26), BS8 and BS16.