Bus event monitor

• US 5,426,741 A
• Filed: 01/14/1994
• Issued: 06/20/1995
• Est. Priority Date: 02/20/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Gillett, Richard B. Jr., Butts, H. Bruce Jr., Leahy, James N.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/182,531
• Time in Patent Office: 522 Days
• Field of Search: 395/575, 395/325, 395/275, 395/425, 395/600
• US Class Current: 710/18
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one. The inactive counter bank is available for reading by the dedicated BEM processor (23) while the counters of the active counter bank are being incremented. Preferably, each counter bank contains a large number of counters (e.g., 64K), each having a large capacity (e.g., 32 bit). As a result, a large number of different events can be counted over an indefinitely long period of time.

Claims

1. A bus event monitor for monitoring the occurrence of events on a computer system bus, said bus event monitor comprising;

a dedicated bus event monitor processor capable of being coupled to a computer system bus, said computer system bus for transmitting packets having a plurality of different types corresponding to a plurality of different events;

an event counter subsystem coupled to said dedicated bus event monitor and capable of being coupled to said computer system bus, said event counter subsystem including;

(i) programmable means, programmable by said dedicated bus event monitor processor, for selecting a subset of said plurality of different types of packets for monitoring by said dedicated bus event monitor;

(ii) means for interpreting said packets transmitted on said computer system bus to determine if the type of each of said transmitted packets is one of said selected subset of different types of packets, and for producing an address that is unique to said type of each of said packets when one of said plurality of interpreted data packets represent one of said plurality of events of interest;

(iii) a first plurality of addressable counters, each of said addressable counters corresponding to one of said selected different types of packets for storing count information of said corresponding type of packet, said first plurality of addressable counters coupled to said programmable means such that a specific counter is accessed when a corresponding address is produced by said programmable means;

(iv) incrementing means coupled to said first plurality of addressable counters for incrementing specific counters each time their corresponding address is produced by said programmable means; and

(v) a second plurality of addressable counters corresponding to said first plurality of addressable counters and for storing count information of said corresponding selected type of packet, said second plurality of addressable counters coupled to said programmable means such that a specific counter is accessed when a corresponding address is produced by said programmable means.

2. The bus event monitor claimed in claim 1, wherein said programmable means comprises a field programmable gate array.

3. The bus event monitor claimed in claim 1, including an input crossbar switch for coupling said programmable means to either said first or said second plurality of addressable counters such that addresses produced by said programmable means are only applied to one of said bank of addressable counters at any time.

4. The bus event monitor claimed in claim 3, wherein said programmable means comprises a field programmable gate array.

5. The bus event monitor claimed in claim 3, including an output crossbar switch coupled to said first and second plurality of addressable counters such that the counters of only one of said first and second plurality of addressable counters are incremented by said incrementing means at any time.

6. The bus event monitor claimed in claim 5, wherein said programmable means comprises a field programmable gate array.

7. The bus event monitor claimed in claim 5, wherein said first and second banks of addressable counters are formed by random access memories.

8. The bus event monitor claimed in claim 7, wherein said programmable means comprises a field programmable gate array.

9. A bus event monitor for monitoring the occurrence of events on a processor bus, said bus event monitor comprising;

a dedicated bus event monitor processor coupled to said processor bus, said processor bus for transmitting packets having a plurality of different types corresponding to a plurality of different events;

an event counter subsystem coupled to said dedicated bus event monitor processor and to said processor bus, said event counter subsystem including;

(i) programable means, programmed by said dedicated bus event monitor processor, for selecting a subset of said plurality of different types of packets for monitoring by said dedicated bus event monitor;

(ii) means for interpreting each of said packets transmitted on said processor bus to determine if the type of each of said transmitted packets is one of said selected subset of different types of packets, and producing an address that is unique to said type of each of said packets when one of said plurality of interpreted packets represent one of said plurality of events of interest;

(iii) a first plurality of addressable counters coupled to said programmable means such that a specific counter is accessed when a corresponding address is produced by said programmable means;

(iv) incrementing means coupled to said first plurality of addressable counters for incrementing the counter that is accessed each time a specific counter is accessed when a corresponding address is produced by said programmable means; and

(v) a second plurality of addressable counters corresponding to said first plurality of addressable counters such that each addressable counter of said second plurality is accessed using said specific address of said addressable counter of said first plurality, said second plurality of addressable counters being coupled to said programmable means such that a specific counter is accessed when a corresponding address is produced by said programmable means.

10. The bus event monitor of claim 9, wherein said programmable means comprises a field programmable gate array.

11. The bus event monitor of claim 10, including an input crossbar switch for coupling said programmable means to either said first or said second plurality of addressable counters such that addresses produced by said programmable means are only applied to one of said bank of addressable counters at any time.

12. The bus event monitor of claim 11, including an output crossbar switch coupled to said first and second plurality of addressable counters such that the counters of only one of said first and second plurality of addressable counters are incremented by said incrementing means at any time.