Memory decoding system for portable data terminal

• US 5,426,753 A
• Filed: 04/25/1994
• Issued: 06/20/1995
• Est. Priority Date: 08/30/1990
• Status: Expired due to Term

• Current Assignee: LG CNS Company Limited (LG Corporation)
• Original Assignee: Gold Star Co., Ltd. (LG Corporation)
• Inventors: Moon, Sung W.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US08/232,577
• Time in Patent Office: 421 Days
• Field of Search: 395/400, 395/425, 365/230.03, 365/230.06, 364/200, 364/900, 364/DIG. 1, 364/DIG. 2
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory decoding system for a portable data terminal includes a memory controller, a memory storage, a first selection signal generator, and a second selection signal generator. The memory controller generates address signals and data signals. The memory storage is divided into a plurality of memory regions, and is controlled in such a manner as to write and read for the specified uses through the memory controller. The first selection signal generator outputs memory selecting signals to select one memory type of the memory storage. The second selection signal generator generates memory selecting signals to select another memory type of the memory storage. The portable terminal can be formed into a more compact type.

Claims

1. A memory decoding system for portable data terminal, comprising:

memory storing means including a plurality of memory regions having a ROM for storing a system program and a plurality of RAMs;

means for selectively generating a memory request signal, address signals and data signals to read data from said memory storing means and to store data into said memory storing means;

first signal generating means for generating first memory selecting signals in order to select one of said memory regions of said memory storing means, said first signal generating means being responsive to a first portion of bits of said address signals and the memory request signal; and

second signal generating means for generating second memory selecting signals in order to select another one of said memory regions of said memory storing means, said second signal generating means being responsive to a second portion of bits of said address signals, said memory request signal, a third portion of bits of said address signals, and a driving voltage signal, said second portion of bits corresponding to different address signals than said first portion of bits,

wherein said first signal generating means and said second signal generating means divides said memory storing means into a system ROM region, a reserve ROM region, a system RAM region, and at least one user RAM region, said second signal generating means including a logic gate responsive to a sub-portion of bits from said second portion of bits of said address signals for producing an output signal, and a decoder receiving a remaining sub-portion of bits from said second portion of bits, the output signal of said logic gate, said memory request signal and said driving voltage signal for generating the second memory selecting signals,

wherein said first signal generating means comprises;

a first logic gate responsive to said first portion of bits of said address signals for producing an output signal; and

a second logic gate for generating a signal in order to select one of said ROM regions of said memory storing means, said second logic gate receiving the output signal of said first logic gate and said memory request signal.

2. The memory decoding system for portable data terminal as claimed in claim 1, wherein said first logic gate is a NAND gate.

3. The memory decoding system for portable data terminal as claimed in claim 1, wherein said second logic gate is an OR gate.

4. The memory decoding system for portable data terminal as claimed in claim 1, wherein said logic gate is an OR gate.