Memory cartridge including a key detector for inhibiting memory access and preventing undesirable write operations

• US 5,426,763 A
• Filed: 05/20/1993
• Issued: 06/20/1995
• Est. Priority Date: 04/20/1989
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Okada, Satoru
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/063,774
• Time in Patent Office: 761 Days
• Field of Search: 365/52, 365/228, 365/229, 365/195, 395/425, 395/575, 395/750, 380/3, 380/4, 273/435
• US Class Current: 711/115
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory cartridge which may be loaded in an attachable/detachable manner to a data processing apparatus, such as a hand-held electronic game machine having a central processing unit (CPU), includes logic control circuitry, a program read only memory (ROM), a bank changing circuit, and external random access memory (RAM). The external RAM is backed-up by a battery. First key data and second key data are initially stored in the program ROM. After a power source of the data processing apparatus is turned-on and a power source voltage reaches a predetermined value, a reset signal is provided to the memory cartridge to enable circuits on the memory cartridge. When the first key data is read from the program ROM and the reset signal is detected, the external RAM may be accessed by the CPU to read and write information from/into the external RAM. When the second key data is read from the program ROM, the CPU is inhibited from such access to the external RAM.

Claims

1. A memory cartridge removably attachable to a data processing apparatus, said memory cartridge comprising:

a random access memory (RAM) for storing data generated by said data processing apparatus;

a read only memory (ROM) for storing a program executable by said data processing apparatus and for storing first multi-bit key data for allowing said data processing apparatus to access said RAM;

holding means for receiving and holding multi-bit key data read from said ROM by said data processing apparatus in accordance with said program;

key detecting means for generating a first key detection signal when said multi-bit key data read from said ROM and held in said holding means corresponds to said first multi-bit key data; and

a control circuit for generating a RAM selection signal for enabling said RAM in response to said first key detection signal and a power detection signal.

2. A memory cartridge in accordance with claim 1, wherein said ROM further stores second multi-bit key data for inhibiting said data processing apparatus from accessing said RAM, and

said key detecting means generates a second key detection signal when multi-bit key data read from said ROM and held in said holding means corresponds to said second key data and

said control circuit inhibits generation of said RAM selection signal to prevent access to said RAM when said second key detection signal is generated by said key detecting means.

3. A memory cartridge in accordance with claim 1, wherein said control circuit generates said RAM selection signal in response to a ROM selection signal from said data processing apparatus in an inactive state in addition to said first key detection signal and said power detection signal in an active state.

4. A memory cartridge in accordance with claim 3, wherein when said data processing apparatus generates a write signal and the RAM selection signal is generated, writing of data into said RAM is enabled.

5. A memory cartridge in accordance with claim 4, wherein when said data processing apparatus further generates a read signal and the RAM selection signal is generated, reading of data from said RAM is enabled.

6. A memory cartridge in accordance with claim 4, wherein said data processing apparatus generates said power detection signal when a voltage to be supplied to said data processing apparatus reaches a predetermined voltage level after a power source is activated.

7. A memory cartridge removably attachable to a data processing apparatus which generates write and read signals, address signals, and execution data for executing a desired program, comprising:

data input terminals for receiving data supplied from said data processing apparatus;

address input terminals for receiving the address signals supplied from said data processing apparatus;

a random access memory (RAM) having data inputs connected to said data input terminals and address inputs connected to said address input terminals;

a read only memory (ROM) for storing said program and first multi-bit key data for allowing said data processing apparatus to access said RAM;

holding means, connected to said data input terminals, for holding multi-bit key data read from said ROM by said data processing apparatus in accordance with said execution data;

key detecting means for generating a first key detection signal when said first multi-bit key data read from said ROM and held in said holding means corresponds to said first key data; and

a control circuit for generating a detection output signal in response to an inactive ROM selection signal, a power detection signal, and said first key detection signal, wherein writing of data into said RAM is enabled in response to said detection output signal and a write signal.

8. A memory cartridge in accordance with claim 7, wherein said ROM further stores second multi-bit key data for inhibiting said data processing apparatus from accessing said RAM,

said key detecting means generates a second key detection signal when data held in said holding means corresponds to said second multi-bit key data, and

said control circuit disables said RAM in response to said second key detection signal.

9. A memory cartridge in accordance with claim 7, wherein said data processing apparatus generates said power detection signal when a voltage to be supplied to said data processing apparatus reaches a predetermined voltage level.

10. A memory cartridge in accordance with claim 7, wherein said memory cartridge is supplied with power from said data processing apparatus upon loading, said memory cartridge further comprising:

a battery for supplying back-up power to said RAM;

a first switch for supplying power to said external RAM from said data processing apparatus; and

a second switch for supplying power from said battery to said RAM when power is not supplied from said data processing apparatus.

11. A memory cartridge in accordance with claim 7, wherein reading of data from said RAM is enabled in response to said detection output signal and a read signal.

12. A memory cartridge in accordance with claim 11, wherein reading of data from said RAM is inhibited when said detection output signal is inactive and reading of data from said ROM is enabled in response at least to said ROM selection signal and said read signal.

13. A memory cartridge in accordance with claim 7, wherein said address input terminals are connected to a plurality of address lines, said ROM is configured with a plurality of memory banks, each bank addressable by said address lines, and said address signals are applied to lower significant bit address lines and bank selection data are applied to upper significant bit address lines.

14. A memory cartridge in accordance with claim 13, wherein said bank selection data are stored in said ROM and are read from said ROM by said data processing apparatus and output to said bank selection data storage means.

15. A memory cartridge removably attachable to a data processing apparatus, comprising:

a random access memory (RAM) for storing data generated by said data processing apparatus;

a read only memory (ROM) for storing program instructions executable by said data processing apparatus, first multi-bit key data for allowing said data processing apparatus to access said RAM, and second multi-bit key data for preventing said data processing apparatus from accessing said RAM;

a register for holding key data read from said ROM by said data processing apparatus in accordance with said program instructions;

a key detector for generating a first key detection signal when said key data read from said ROM and held in said register corresponds to said first multi-bit key data and a second key detection signal when said key data read from said ROM and held in said register corresponds to said second multi-bit key data;

a control circuit for enabling said RAM at least in part in response to said first key detection signal to permit said data processing apparatus to write data into said RAM and for disabling said RAM in response to said second key detection signal.

16. A memory cartridge in accordance with claim 15, wherein said first key data is applied to said register from said ROM before said data processing apparatus writes data into said RAM, and said second key data is applied to said register from said ROM after completion of writing of data into said RAM by said data processing apparatus.

17. A memory cartridge according to claim 15, wherein said control circuit enables said RAM at least in part in response to said first key detection signal and a ROM selection signal from said data processing apparatus in an active state.

18. A memory cartridge according to claim 15, wherein said control circuit enables said RAM at least in part in response to a signal representative of a voltage level of a power source voltage supplied to the data processing apparatus.