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Latent defect handling in EEPROM devices

  • US 5,428,621 A
  • Filed: 09/21/1992
  • Issued: 06/27/1995
  • Est. Priority Date: 09/21/1992
  • Status: Expired due to Term
First Claim
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1. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein a word line thereamong is connected to the control gates of each row of memory cells, and a pair of bit lines thereamong are respectively connected to the sources and the drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, said integrated circuit memory device further comprising:

  • a word line leakage detector for measuring leakage current in a word line connectable thereto; and

    means for connecting said word line leakage detector to a word line under test to measure the leakage current therein, whereby a defective word line is identifiable by said leakage current exceeding a predetermined level.

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