Latent defect handling in EEPROM devices

• US 5,428,621 A
• Filed: 09/21/1992
• Issued: 06/27/1995
• Est. Priority Date: 09/21/1992
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Gross, Stephen J., Lee, Winston, Mehrotra, Sanjay, Samachisa, George
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/948,175
• Time in Patent Office: 1,009 Days
• Field of Search: 371/21.4, 371/21.6, 371/10.1-10.3, 365/184, 365/185, 365/200, 365/201, 324/158 T
• US Class Current: 714/721
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connected respectively to all the sources and drains of each column of cells. The memory system incorporates a word line current detector and an erase line current detector in addition to the usual bit line current detectors. The leakage current of each of the lines are measured after predetermined memory events such as program or erase operations. When a defective row or column is detected, it is electrically isolated from other columns by programming and is mapped out and replaced. Data recovery schemes include reading a defective column by a switched-memory-source-drain technique.

Claims

1. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein a word line thereamong is connected to the control gates of each row of memory cells, and a pair of bit lines thereamong are respectively connected to the sources and the drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, said integrated circuit memory device further comprising:

a word line leakage detector for measuring leakage current in a word line connectable thereto; and

means for connecting said word line leakage detector to a word line under test to measure the leakage current therein, whereby a defective word line is identifiable by said leakage current exceeding a predetermined level.

2. An integrated circuit memory device as in claim 1, wherein the memory cell being of the type including an erase electrode, and said access lines include erase lines, wherein an erase line is connected to the erase electrodes of each sector of cells consisting of one or more rows of memory cells, said integrated circuit memory device further comprising:

a erase line leakage detector for measuring leakage current in an erase line connectable thereto; and

means for connecting said erase line leakage detector to an erase line under test to measure the leakage current therein, whereby a defective erase line is identifiable by said leakage current exceeding a predetermined level.

3. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

providing a word line leakage detector within said memory device;

establishing under the control of said memory controller a predetermined potential difference for a word line under test relative to the substrate and a set of access lines that are capable of being shorted to said word line under test;

using said word line leakage detector under the control of said memory controller to detect a short circuit condition at said word line under test when a leakage current measured therein exceeded a predetermined level; and

repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every word line to be tested in the EEPROM memory array.

4. A method for detecting word line defects in an EEPROM memory array as in claim 3, wherein the method is applied to a set of word lines under test simultaneously.

5. A method for detecting defects among a set of word lines in an EEPROM memory array as in claim 4, wherein said set of word lines includes all the word lines in the EEPROM memory array.

6. A method for detecting word line defects in an EEPROM memory array as in claim 3, wherein said method is implemented during use of the EEPROM memory array at preselected times.

7. A method for detecting word line defects in an EEPROM memory array as in claim 6, wherein the method is applied to a set of word lines under test simultaneously.

8. A method for detecting defects among a set of word lines in an EEPROM memory array as in claim 7, wherein said set of word lines consists of all the word lines in the EEPROM memory array.

9. A method for detecting word line defects in the EEPROM memory array as in claim 3, wherein:

the memory cell is of the type including an erase electrode;

the memory array is organized into sectors of cells consisting of one or more rows of cells that are erasable together; and

the access lines include erase lines connected to the erase electrodes of each sector of cells.

10. A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes grounding a set of access lines that are capable of being shorted to said word line under test, so as to determine if the word line under test is shorted to the substrate or any one of said set of access lines.

11. A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the word lines therein while floating the erase lines and bit lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the word lines therein.

12. A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the bit lines therein while floating the word lines and erase lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the bit lines therein.

13. A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the erase lines therein while floating the word lines and bit lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the erase lines therein.

14. A method for detecting word line defects in an EEPROM memory array as in claim 9, further including a sequence of tests such that in each test the step of raising the word line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as word lines or bit lines therein, so as to identify what type of line the word line under test is shorted to.

15. A method for detecting word line defects in an EEPROM memory array as in claim 3, further including a sequence of tests such that in each test the step of raising the word line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as word lines or bit lines therein, so as to identify what type of line the word line under test is shorted to.

16. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

establishing under the control of said memory controller a predetermined potential difference for a bit line under test relative to the substrate and a set of access lines that are capable of being shorted to said bit line under test;

detecting under the control of said memory controller a short circuit condition at said bit line under test when a leakage current measured therein exceeded a predetermined level; and

repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every bit line to be tested in the EEPROM memory array.

17. A method for detecting bit line defects in an EEPROM memory array as in claim 16, wherein the method is applied to a set of bit lines under test simultaneously.

18. A method for detecting defects among a set of bit lines in an EEPROM memory array as in claim 16, wherein said set of bit lines includes all the bit lines in the EEPROM memory array.

19. A method for detecting bit line defects in an EEPROM memory array as in claim 16, wherein said method is implemented during use of the EEPROM memory array at preselected times.

20. A method for detecting bit line defects in an EEPROM memory array as in claim 19, wherein the method is applied to a set of bit lines under test simultaneously.

21. A method for detecting defects among a set of bit lines in an EEPROM memory array as in claim 20, wherein said set of bit lines consists of all the bit lines in the EEPROM memory array.

22. A method for detecting bit line defects in the EEPROM memory array as in claim 16, wherein:

the memory cell is of the type including an erase electrode;

the memory array is organized into sectors of cells consisting of one or more rows of cells that are erasable together; and

the access lines include erase lines connected to the erase electrodes of each sector of cells.

23. A method for detecting bit line defects in the EEPROM memory array as in claim 22, wherein the step of raising the bit line under test to a predetermined potential includes grounding a set of access lines that are capable of being shorted to said bit line under test, so as to determine if the bit line under test is shorted to the substrate or any one of said set of access lines.

24. A method for detecting bit line defects in the EEPROM memory array as in claim 22, wherein the step of raising the bit line under test to a predetermined potential includes, among said set of access lines, grounding the bit lines therein while floating the erase lines and word lines therein, so as to determine if the bit line under test is shorted to the substrate or any one of the bit lines therein.

25. A method for detecting bit line defects in the EEPROM memory array as in claim 22, wherein the step of raising the bit line under test to a predetermined potential includes, among said set of access lines, grounding the word lines therein while floating the bit lines and erase lines therein, so as to determine if the bit line under test is shorted to the substrate or any one of the word lines therein.

26. A method for detecting bit line defects in the EEPROM memory array as in claim 22, wherein the step of raising the bit line under test to a predetermined potential includes, among said set of access lines, grounding the erase lines therein while floating the bit lines and word lines therein, so as to determine if the bit line under test is shorted to the substrate or any one of the erase lines therein.

27. A method for detecting bit line defects in an EEPROM memory array as in claim 22, further including a sequence of tests such that in each test the step of raising the bit line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as bit lines or word lines therein, so as to identify what type of line the bit line under test is shorted to.

28. A method for detecting bit line defects in an EEPROM memory array as in claim 16, further including a sequence of tests such that in each test the step of raising the bit line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as bit lines or word lines therein, so as to identify what type of line the bit line under test is shorted to.

29. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting erase line defects in the EEPROM memory array comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

providing a erase line leakage line detector within said memory device;

establishing under the control of said memory controller a predetermined potential difference for a erase line under test relative to the substrate and a set of access lines that are capable of being shorted to said erase line under test;

using said erase line leakage detector under the control of said memory controller to detect a short circuit condition at said erase line under test when a leakage current measured therein exceeded a predetermined level; and

repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every erase line to be tested in the EEPROM memory array.

30. A method for detecting erase line defects in an EEPROM memory array as in claim 29, wherein the method is applied to a set of erase lines under test simultaneously.

31. A method for detecting defects among a set of erase lines in an EEPROM memory array as in claim 30, wherein said set of erase lines includes all the erase lines in the EEPROM memory array.

32. A method for detecting erase line defects in an EEPROM memory array as in claim 29, wherein said method is implemented during use of the EEPROM memory array at preselected times.

33. A method for detecting erase line defects in an EEPROM memory array as in claim 32, wherein the method is applied to a set of erase lines under test simultaneously.

34. A method for detecting defects among a set of erase lines in an EEPROM memory array as in claim 33, wherein said set of erase lines consists of all the erase lines in the EEPROM memory array.

35. A method for detecting erase line defects in the EEPROM memory array as in claim 29, wherein the step of raising the erase line under test to a predetermined potential includes grounding a set of access lines that are capable of being shorted to said erase line under test, so as to determine if the erase line under test is shorted to the substrate or any one of said set of access lines.

36. A method for detecting erase line defects in the EEPROM memory array as in claim 29, wherein the step of raising the erase line under test to a predetermined potential includes, among said set of access lines, grounding the erase lines therein while floating the word lines and bit lines therein, so as to determine if the erase line under test is shorted to the substrate or any one of the erase lines therein.

37. A method for detecting erase line defects in the EEPROM memory array as in claim 29, wherein the step of raising the erase line under test to a predetermined potential includes, among said set of access lines, grounding the bit lines therein while floating the erase lines and word lines therein, so as to determine if the erase line under test is shorted to the substrate or any one of the bit lines therein.

38. A method for detecting erase line defects in the EEPROM memory array as in claim 29, wherein the step of raising the erase line under test to a predetermined potential includes, among said set of access lines, grounding the word lines therein while floating the erase lines and bit lines therein, so as to determine if the erase line under test is shorted to the substrate or any one of the erase lines therein.

39. A method for detecting erase line defects in an EEPROM memory array as in claim 29, further including a sequence of tests such that in each test the step of raising the erase line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as erase lines or bit lines therein, so as to identify what type of line the erase line under test is shorted to.

40. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting defects in a specified type of access line in the EEPROM memory array comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

providing a leakage detector within said memory device

establishing under the control of said memory controller a predetermined potential difference for an access line under test of said specified type relative to the substrate and a set of access lines that are capable of being shorted to said access line under test;

using said leakage detector under the control of said memory controller to detect a short circuit condition at said access line under test when a leakage current measured therein exceeded a predetermined level; and

repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every access line of said specified type to be tested in the EEPROM memory array.

41. A method for detecting defects in a specified type of access line in the EEPROM memory array as in claim 40, wherein the method is applied to a set of access lines of said specified type under test simultaneously.

42. A method for detecting defects in a set of specified type of access line in an EEPROM memory array as in claim 41, wherein said set includes all access lines of said specified type in the EEPROM memory array.

43. A method for detecting defects in a specified type of access line in an EEPROM memory array as in claim 40, wherein said method is implemented during use of the EEPROM memory array at preselected times.

44. A method for detecting defects in a specified type of access line in the EEPROM memory array as in claim 43, wherein the method is applied to a set of access lines of said specified type under test simultaneously.

45. A method for detecting defects in a set of specified type of access line in an EEPROM memory array as in claim 44, wherein said set includes all access lines of said specified type in the EEPROM memory array.

46. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to a bit line shorted to another type of access line in the EEPROM memory array, comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

powering under the control of said memory controller a pair of bit lines in a column under test to voltage conditions for reading while keeping all other bit lines in the EEPROM memory array floated and all word lines and erase lines grounded;

detecting under the control of said memory controller a short circuit condition at said pair of bit lines under test when a leakage current measured therein exceeded a predetermined level; and

repeating the steps of powering and detecting for the pair of bit lines in every column to be tested in the EEPROM memory array.

47. A method for detecting column defects due to a bit line shorted to another type of access line in the EEPROM memory array as in claim 46, wherein said method is implemented during use of the EEPROM memory array at preselected times.

48. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

powering under the control of said memory controller a pair of bit lines in each column among a set of columns simultaneously under test to voltage conditions for reading while keeping all word lines grounded and all other bit lines floated;

detecting under the control of said memory controller a short circuit condition at the pair of bit lines in each column among the set of columns simultaneously under test when a leakage current measured in the pair of bit lines exceeded a predetermined level; and

repeating the steps of powering and detecting for every set of columns simultaneously under test in the EEPROM memory array.

49. A method for detecting column defects in an EEPROM memory array as in claim 48, wherein the set of columns simultaneously under test consists of one column in the EEPROM memory array.

50. A method for detecting column defects in an EEPROM memory array as in claim 48, wherein the set of columns simultaneously under test consists of alternate columns in the EEPROM memory array.

51. A method for detecting column defects due to bit line short circuit in the EEPROM memory array as in claim 48, wherein said method is implemented during use of the EEPROM memory array at preselected times.

52. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

providing a memory controller for controlling memory operations of said memory device;

maintaining at least one row of cells all pre-programmed to a memory state corresponding substantially to a minimum conduction current through the source and drain of each cell during a read operation;

detecting under the control of said memory controller any short circuit condition at a column by reading the programmed memory state in each of said at least one row of cells therein and determining if the pair of bit lines in the column has a conduction current substantially more than said minimum current; and

repeating the steps of reading and detecting for every column to be tested in the EEPROM memory array.

53. A method for detecting column defects due to bit line short circuit in the EEPROM memory array as in claim 52, wherein said method is applied to a set of columns at a time.

54. A method for detecting column defects due to bit line short circuit in the EEPROM memory array as in claim 52, wherein said method is implemented during use of the EEPROM memory array at preselected times.

55. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

providing a memory controller for controlling memory operations of said nenory device;

maintaining at least one row of cells all pre-erased to a memory state corresponding to substantially a maximum conduction current through the source and drain of each cell during a read operation;

detecting under the control of said memory controller any short circuit condition at a column by reading the programmed memory state in each of said at least one row of cells therein and determining if the pair of bit lines in the column has a conduction current substantially less than said maximum conduction current; and

repeating the steps of reading and detecting for every column to be tested in the EEPROM memory array.

56. A method for detecting column defects due to bit line short circuit in the EEPROM memory array as in claim 55, wherein said method is applied to a set of columns at a time.

57. A method for detecting column defects due to bit line short circuit in the EEPROM memory array as in claim 55, wherein said method is implemented during use of the EEPROM memory array at preselected times.

58. In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for handling defects in the EEPROM memory array comprising providing a memory controller for controlling memory operations of said memory device, said memory controller performing the steps of:

detecting any defective access line of the memory array by measuring therein a leakage current that exceeds a predetermined level;

recovering the data from defective memory cells in said defective access line;

mapping out the defective memory cells in said defective access line and replacing with substitute memory cells;

replacing the recovered data in the substitute memory cells.

59. A method for handling defects in the EEPROM memory array as in claim 58, wherein said method is implemented during use of the EEPROM memory array at preselected times.

60. A method for handling defects in the EEPROM memory array as in claim 58, wherein said defective access line is a bit line and results in a defective column containing said defective bit line.

61. A method for handling defects in the EEPROM memory array as in claim 60, further comprising:

electrically isolating the defective memory cells in said defective bit line by programming each of said defective memory cells whose drain is connected by the defective bit line to a memory state corresponding to a minimum source to drain conduction current.

62. A method for handling defects in the EEPROM memory array as in claim 60, further comprising:

electrically isolating the defective memory cells in said defective bit line by programming one or more cells in adjacent columns to each of said defective memory cells a memory state corresponding to a minimum source to drain conduction current.

63. A method for handling defects in the EEPROM memory array as in claim 60, wherein the step of recovering the data from memory cells in a defective column resulting from a short circuit of a drain line thereof to a word line or an erase line or substrate includes reading the data from memory cells in said defective column by interchanging the potential applied to the source line and the drain line therein.

64. A method for handling defects in the EEPROM memory array as in claim 62, further comprising:

determining whether the defective bit line is shorted to another bit line or to a word line or an erase line or substrate, wherein the steps of recovering the data, mapping out, replacing the recovered data and electrically isolating apply to;

all cells in the defective column when the defective bit line is shorted to a word line, erase line or substrate; and

at least the defective cells in the defective column when the defective bit line is shorted to another bit line.