Circuitry and method for sharing internal microcontroller memory with an external processor

• US 5,428,760 A
• Filed: 02/06/1992
• Issued: 06/27/1995
• Est. Priority Date: 12/12/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ghori, Amar, McIntyre, Steven M., Lambert, Herve R.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/831,896
• Time in Patent Office: 1,237 Days
• Field of Search: 395/400, 395/425
• US Class Current: 711/149
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

Methods and circuitry for sharing a memory space of a microcontroller with a processor. The memory space corresponds to a random access memory accessible by the microcontroller. The memory space includes random access memory on a same substrate as the microcontroller. The processor is located on a different substrate from the microcontroller. The circuitry includes a slave port for communicating data between the processor and the microcontroller. The slave port receives a logical address and a control signal from the processor. The slave port generates an interrupt signal in response to the control signal. An interrupt server generates memory control signals in response to the interrupt signal. A memory controller reads data from and writes data to the slave port and a memory location associated with the logical address in response to the memory control signals.

Claims

1. Microcontroller circuitry for sharing a memory space of a microcontroller with a processor, comprising:

a) a slave port for communicating data between the processor and the microcontroller wherein the processor is located on a different substrate from the microcontroller, the slave port receiving a logical address and a control signal from the processor, wherein the logical address is associated with a memory location in the memory space, the slave port generating an interrupt signal in response to the control signal;

b) an interrupt server for generating memory control signals in response to the interrupt signal; and

c) a memory controller for reading data from and writing data to the slave port and the memory location in the memory space in response to the memory control signals, wherein the memory space corresponds to a random access memory accessible by the microcontroller, wherein a shared memory space includes random access memory on a same substrate as the microcontroller.

2. The microcontroller circuitry of claim 1 wherein the interrupt server comprises:

a) circuitry for reading a status register pointed to by a slave pointer;

b) circuitry for determining a type of memory access requested by the processor;

c) circuitry for determining a physical address of the memory location associated with the logical address; and

d) circuitry for generating the memory control signals.

3. The microcontroller circuitry of claim 2 wherein the circuitry for determining the physical address of the memory concatenates the logical address with a base address stored in a control block in the memory space.

4. The microcontroller circuitry of claim 2 wherein the interrupt server further comprises microcode.

5. The microcontroller circuitry of claim 2, wherein the microcontroller and the processor utilize a multiplexed address/data communications protocol.

6. The microcontroller circuitry of claim 2 wherein the slave port further comprises:

a) an address register coupled to receive the logical address;

b) a data register for storing data communicated between the processor and the microcontroller;

c) control logic for generating register control signals in response to the control signal from the processor; and

d) an interrupt generator for generating the interrupt signal in response to the register control signals;

7. The circuitry of claim 6 wherein the data register comprises:

a) a data input register for receiving data to be written to the memory from the processor;

b) a data output register for providing data read from the memory to the processor.

8. The microcontroller circuitry of claim 6 wherein the slave port further comprises the status register coupled to the control logic and the interrupt generator for indicating the status of the slave port to the interrupt server.

9. The microcontroller circuitry of claim 2 wherein the slave port is a logical port utilizing a pre-existing input/output port of the microcontroller.

10. A method of sharing a memory space of a microcontroller with a processor, comprising the steps of:

a) providing a logical address originating from the processor to a slave port of the microcontroller;

b) providing a memory access request from the processor to the slave port of the microcontroller;

c) storing a received data value from the processor in a data register accessible by the processor if the memory access request is a write request;

d) generating a physical address of a memory location in the memory space from the logical address, wherein the physical address corresponds to a random access memory in the memory space accessible by the microcontroller, wherein the memory space includes random access memory residing on a same substrate as the microcontroller;

e) storing a retrieved data value from the physical address in the data register if the memory access request is a read request; and

f) storing the received data value from the data register in the memory location if the memory access request is a write request.

11. A method of sharing a memory space of a microcontroller with a processor, comprising the steps of:

a) storing a base address in a control block in the memory space;

b) storing a count representing the number of pending memory access operations requested in a count field of the control block;

c) determining a physical address corresponding to a logical address provided by the processor to a slave port of the microcontroller, wherein the physical address corresponds to a random access memory in the memory space accessible by the microcontroller, wherein the memory space includes random access memory residing on a same substrate as the microcontroller;

d) determining a type of a memory access request provided by the processor to the slave port;

e) executing the memory access request;

f) decrementing the count stored in the count field; and

g) repeating steps e) and f) until the count represents that no more memory access operations are pending.

12. The method of claim 11 wherein the step of determining a physical address of the logical address comprises concatenating the base address and the logical address.

13. The method of claim 11 wherein the step of executing the memory access request for a read request further comprises the steps:

1) retrieving a data value located at the physical address; and

2) storing the data value in a data register accessible by the processor.

14. The method of claim 11 wherein the step of executing the memory access request for a write request further comprises the steps:

1) retrieving a data value provided by the processor from a data register; and

2) storing the data value at the physical address.

15. The method of claim 11 further comprising the step of:

h) resetting the base address to a default page.

16. The method of claim 15 wherein the processor can access the control block only when the base address is set to the default page.

17. The method of claim 16 wherein the base address is reset by a user-programmed software routine in response to a software interrupt signal generated by the slave port when the count represents that no more memory access operations are pending.