Error detection scheme in a multiprocessor environment
First Claim
1. A computer system, which comprises:
- a plurality of source devices, each one of the plurality of source devices being a source of messages;
a plurality of destination devices, each one of the plurality of destination devices being a destination of messages;
a common memory comprising a plurality of buffers for storing messages from any one of the plurality of source devices for passing to any of the plurality of destination devices,a system bus for coupling each one of the plurality of source and destination devices to each other and to the common memory;
a pool of pointers to buffers of the common memory that are available for use to store messages;
a plurality of pointer memories coupled to each one of the plurality of source and destination devices, each one of the plurality of pointer memories being associated with a particular pair of source and destination devices,each pointer memory having a set of locations for storing pointers to buffers of the common memory; and
one particular source device of the plurality of source devices transferring a message to one particular destination device of the plurality of destination devices by writing the message to one of the plurality of buffers, and writing the pointer to the one of the plurality of buffers to a preselected location of the pointer memory associated with the particular source and destination device pair,the particular destination device reading the pointer to the one of the plurality of buffers from the preselected location of the pointer memory;
a buffer interchange observer coupled to the plurality of source and destination devices and to the central memory by the system bus, the buffer interchange observer comprising a pointer memory protocol monitor monitoring accesses to the pointer memories and checking that only the particular source and destination devices associated with a particular pointer memory access the particular pointer memory.
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Accused Products
Abstract
An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processor computer system implementing a buffer swapping scheme. The error detection scheme of the present invention provides for the monitoring of bus transactions, maintaining a log of bus activity including buffer access transactions, identifying transactions involving buffer and address recognition operations and checking those operations to insure that they are consistent with the implemented buffer swapping scheme. Upon detection of an error the bus monitoring device asserts an error signal, freezes the log of bus activity and halts buffer swapping activity until the detected error is investigated and dealt with in an appropriate manner.
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Citations
24 Claims
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1. A computer system, which comprises:
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a plurality of source devices, each one of the plurality of source devices being a source of messages; a plurality of destination devices, each one of the plurality of destination devices being a destination of messages; a common memory comprising a plurality of buffers for storing messages from any one of the plurality of source devices for passing to any of the plurality of destination devices, a system bus for coupling each one of the plurality of source and destination devices to each other and to the common memory; a pool of pointers to buffers of the common memory that are available for use to store messages; a plurality of pointer memories coupled to each one of the plurality of source and destination devices, each one of the plurality of pointer memories being associated with a particular pair of source and destination devices, each pointer memory having a set of locations for storing pointers to buffers of the common memory; and one particular source device of the plurality of source devices transferring a message to one particular destination device of the plurality of destination devices by writing the message to one of the plurality of buffers, and writing the pointer to the one of the plurality of buffers to a preselected location of the pointer memory associated with the particular source and destination device pair, the particular destination device reading the pointer to the one of the plurality of buffers from the preselected location of the pointer memory; a buffer interchange observer coupled to the plurality of source and destination devices and to the central memory by the system bus, the buffer interchange observer comprising a pointer memory protocol monitor monitoring accesses to the pointer memories and checking that only the particular source and destination devices associated with a particular pointer memory access the particular pointer memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A computer system, which comprises:
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a plurality of source devices, each one of the plurality of source devices being a source of messages; a plurality of destination devices, each one of the plurality of destination devices being a destination of messages; a common memory comprising a plurality of buffers for storing messages from any one of the plurality of source devices for passing to any of the plurality of destination devices, a system bus for coupling each one of the plurality of source and destination devices to each other and to the common memory; a pool of pointers to buffers of the common memory that are available for use to store messages; an access recognition engine coupled to the plurality of source and destination devices by the system bus, the access recognition engine including a request/response RAM for storing access recognition requests and responses to the requests, the request/response RAM including a plurality of memory locations, each memory location being associated with a particular one of the plurality of source devices; a plurality of pointer memories coupled to each one of the plurality of source and destination devices, each one of the plurality of pointer memories being associated with a particular pair of source and destination devices, each pointer memory having a set of locations for storing pointers to buffers of the common memory; and one particular source device of the plurality of source devices accessing the address recognition engine to determine which one particular destination device of the plurality of destination devices to transfer a message to, the one particular source device transferring the message to the one particular destination device by writing the message to one of the plurality of buffers, and writing the pointer to the one of the plurality of buffers to a preselected location of the pointer memory associated with the particular source and destination device pair, the particular destination device reading the pointer to the one of the plurality of buffers from the preselected location of the pointer memory; and an access recognition engine checker coupled to the plurality of source and destination devices and the common memory by the system bus, the access recognition engine checker checking that any device accessing a particular request/response RAM memory location is the particular source device associated with the particular request/response RAM memory location.
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23. A computer system, which comprises:
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a plurality of source devices, each one of the plurality of source devices being a source of messages; a plurality of destination devices, each one of the plurality of destination devices being a destination of messages; a common memory comprising a plurality of buffers for storing messages from any one of the plurality of source devices for passing to any of the plurality of destination devices, a system bus for coupling each one of the plurality of source and destination devices to each other and to the common memory; a pool of pointers to buffers of the common memory that are available for use to store messages; a plurality of pointer memories coupled to each one of the plurality of source and destination devices, each one of the plurality of pointer memories being associated with a particular pair of source and destination devices, each pointer memory having a set of locations for storing pointers to buffers of the common memory, each location of the pointer memory including an ownership field having a first state and a second state, the first state indicating that the corresponding location is owned by the source processor, and stores a pointer to a buffer that is owned by the source device associated with the particular pointer memory, the stored pointer being valid for use by the source device to store a message, and the second state indicating that the corresponding destination device owns the particular pointer memory location and that the corresponding location stores a pointer to a buffer owned by the destination device associated with the particular pointer location, the stored pointer being valid for use by the destination device to read a message at the buffer of the common memory pointed to by the pointer, the particular source and destination devices associated with the particular pointer memory location operating to change the state of the ownership field as pointers to messages are exchanged between the source and destination devices; one particular source device of the plurality of source devices transferring a message to one particular destination device of the plurality of destination devices by writing the message to one of the plurality of buffers, and writing the pointer to the one of the plurality of buffers to a preselected location of the pointer memory associated with the particular source and destination device pair, the particular destination device reading the pointer to the one of the plurality of buffers from the preselected location of the pointer memory; a buffer interchange observer coupled to the plurality of source and destination devices and to the central memory by the system bus, the buffer interchange observer comprising a buffer rights table including information on buffer ownership, and a buffer operations checker, the buffer operations checker using the information contained in the buffer rights table and to check that a particular device accessing a particular buffer in common memory owns the particular buffer.
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24. A method of detecting errors in a multiprocessor computer system implementing a buffer swapping scheme for communicating messages between a plurality of source and destination devices, the computer system having a common memory comprising a plurality of buffers coupled to the plurality of source and destination devices by a system bus, the method comprising the steps of:
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creating a pool of pointers to the buffers in the common memory that are available for use to store messages; associating each one of a plurality of pointer memories with a particular pair of the plurality of source and destination devices, each pointer memory having a set of locations for storing pointers to the buffers of the common memory; storing a message from a particular one of the plurality of source devices, for passing to a particular one of the plurality of destination devices, in one of the plurality of buffers of the common memory; writing the pointer to the one of the plurality of buffers to a preselected location of the pointer memory associated with the particular source and destination device pair; and monitoring accesses to the pointer memories and checking that only the particular source and destination devices associated with a particular pointer memory access the particular pointer memory.
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Specification