Radiation-emitting diode with improved radiation output

• US 5,429,954 A
• Filed: 11/08/1993
• Issued: 07/04/1995
• Est. Priority Date: 02/20/1993
• Status: Expired due to Term

• Current Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Original Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Inventors: Gerner, Jochen
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/148,856
• Time in Patent Office: 603 Days
• Field of Search: 437/209, 437/23, 437/977, 437/207, 437/208, 437/247, 437/904, 437/905, 437/906, 148/DIG. 138, 148/DIG. 99, 148/DIG. 80, 257/620, 257/623, 257/625, 257/626, 257/13, 257/14
• US Class Current: 438/33
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

A method for manufacture of radiation-emitting diodes includes manufacturing a layer sequence containing a radiation-generating pn-junction on a substrate wafer manufacturing contact layers for electrical connections on an upper face of the layer sequence and on an underside of the substrate wafer, etching trenches defining the size and shape of the area of individual pn-junctions of individual diodes being manufactured, providing a protective layer extending over the upper face contact layers and the etched trenches, subdividing the wafer having the layer sequence, the contact layers, and the protective layer thereon into individual diodes having lateral faces, after the subdividing, etching the lateral faces which are not provided with the protective layer to make the lateral faces into rough surfaces, and removing the protective layer following etching of the lateral faces.

Claims

1. A method for manufacture of radiation-emitting diodes, comprising:

manufacturing a layer sequence containing a radiation-generating pn-junction on a substrate wafer;

manufacturing contact layers for electrical connections on an upper face of said layer sequence and on an underside of said substrate wafer;

etching trenches defining the size and shape of the area of individual pn-junctions of individual diodes being manufactured;

providing protective layer extending over said upper face contact layers and said etched trenches;

subdividing said wafer having said layer sequence, said contact layers, and said protective layer thereon into individual diodes having lateral faces;

after said subdividing, etching only said lateral faces which are not provided with said protective layer to make said lateral faces into rough surfaces; and

removing said protective layer following etching of said lateral faces.

2. A method according to claim 1, wherein said substrate wafer and said layer sequence containing said pn-junction consist of a III-V compound semiconductor material.

3. A method according to claim 1, wherein said protective layer consists of silicon dioxide.

4. A method according to claim 3, wherein said step of providing a silicon dioxide protective layer comprises providing said silicon dioxide protective layer by chemical vapor deposition.

5. A method according to claim 4, wherein said chemical vapor deposition of said silicon dioxide protective layer comprises thermal chemical vapor deposition with silane SiH4 and oxygen O2 as basic substances.

6. A method according to claim 3, wherein said step of providing a silicon dioxide protective layer comprises providing said silicon dioxide protective layer by plasma-enhanced chemical vapor deposition with silane SiH4 and nitrous oxide N2O as basic substances at a temperature of between 250°

C. and 350°

C.

7. A method according to claim 6, wherein said silicon dioxide protective layer is deposited with a thickness of between 150 and 1500 nm.

8. A method according to claim 1, wherein said step of etching of said lateral faces is provided in an etching solution comprising 65% nitric acid HNO3 at room temperature.

9. A method according to claim 1, wherein said step of etching of said lateral faces comprises performing a dry etching process.

10. A method according to claim 1, further comprising during said step of etching of said lateral faces, affixing said contact layer on said underside of said substrate wafer onto a carrier foil.

11. A method according to claim 10, wherein said step of affixing to said carrier foil is performed prior to said step of subdividing.

12. A method according to claim 8, further comprising during said step of etching of said lateral faces, affixing said contact layer on said underside of said substrate wafer onto a carrier foil.

13. A method according to claim 12, wherein said step of affixing to said carrier foil is performed prior to said step of subdividing.

14. A method according to claim 13, wherein said step of removing said protective layer is performed following said step of etching of said lateral faces.

15. A method according to claim 9, further comprising during said step of etching of said lateral faces, affixing said contact layer on said underside of said substrate wafer onto a carrier foil.

16. A method according to claim 15, wherein said step of affixing to said carrier foil is performed prior to said step of subdividing.