Low on-resistance power MOS technology

• US 5,429,964 A
• Filed: 01/12/1994
• Issued: 07/04/1995
• Est. Priority Date: 12/21/1990
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Chang, Mike, Yilmaz, Hamza, Owyang, King, Pitzer, Dorman C., Chen, Jun W., Van Der Linde, Jan
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/180,265
• Time in Patent Office: 538 Days
• Field of Search: 437/41, 437/154, 437/27-30, 257/335-338
• US Class Current: 438/268
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

Claims

1. A method of fabricating a MOSFET, comprising the steps of:

providing a semiconductor body of a first conductivity type with (a) a lightly doped well region of a second conductivity type opposite to the first conductivity type and (b) a surface-adjoining body contact region of the second conductivity type such that said body contact region is continuous with, and more heavily doped than, said well region;

creating a patterned gate electrode over a dielectric layer formed along said semiconductor body; and

providing said semiconductor body with (a) a surface-adjoining body region of the second conductivity type and (b) a surface-adjoining source of the first conductivity type such that said body region is continuous with said well region and extends beyond its lateral periphery under said gate electrode, the three regions of the second conductivity type forming a surface-adjoining composite region of the second conductivity type where said source is situated in part of said composite region and is spaced apart from semiconductor material of said semiconductor body outside said composite region.

2. A method as in claim 1 wherein the second providing step entails furnishing said semiconductor body with an annular surface-adjoining channel that extends below said gate electrode from said source to semiconductor material of said semiconductor body outside said composite region, both the inner and outer periphery of the channel being generally in the shape of a polygon having more than four sides, each interior angle that joins two of the sides being at least 120 degrees.

3. A method as in claim 2 wherein each polygon has an even number of sides, half of which are longer than the other half, each longer side joining two of the shorter sides.

4. A method as in claim 1 wherein said body contact region is also more heavily doped than said body region.

5. A method as in claim 4 wherein said well region extends into said semiconductor body to a greater depth than said body contact and body regions.

6. A method as in claim 1 wherein a dopant is introduced through a mask window into said semiconductor body during the first providing step to form said body contact region by a procedure that comprises (a) covering the mask window with a doping layer that contains the dopant and (b) causing the dopant to diffuse from the doping layer into said semiconductor body.

7. A method as in claim 1 wherein the first providing step comprises separately introducing first and second dopants of the second conductivity type into said semiconductor body such that the first dopant forms said well region, and the second dopant forms the body contact region.

8. A method as in claim 7 wherein the second dopant is introduced through a first mask window into said semiconductor body by a procedure that comprises (a) covering the first mask window with a doping layer that contains the second dopant and (b) causing the second dopant to diffuse from the doping layer into said semiconductor body.

9. A method as in claim 7 wherein the first dopant is introduced into said semiconductor body before the second dopant.

10. A method as in claim 7 wherein the second providing step comprises (a) introducing a third dopant of the second conductivity type into said semiconductor body through a second mask window substantially bounded by said gate electrode such that the third dopant forms said body region and (b) introducing a dopant of the first conductivity type into said semiconductor body through a third mask window consisting substantially of part of the second mask window.

11. A method as in claim 10 wherein the second mask window is generally in the shape of a polygon having more than four sides, each interior angle that joins two of the sides being at least 120 degrees.

12. A method as in claim 11 wherein the polygon has an even number of sides, half of which are longer than the other half, each longer side joining two of the shorter sides.

13. A method as in claim 12 wherein the number of longer sides is four, each interior angle being approximately 135 degrees.

14. A method as in claim 10 wherein the third mask window is in the shape of an annulus whose outer periphery is substantially formed by said gate electrode and whose inner periphery is formed by a separate mask portion.

15. A method of forming an integrated circuit MOSFET cell in a silicon body of a first conductivity type, comprising the steps of:

forming a first mask over said silicon body;

opening a first window that extends at least partially through said first mask over a dopant-introduction site of said silicon body;

forming a lightly doped well of a second conductivity type opposite to said first conductivity type aligned with said first window;

diffusing dopant in said lightly doped well laterally and outwardly away from said first window so as to expand said lightly doped well;

forming a heavily doped region of said second conductivity type aligned with said first window, said heavily doped region being formed within said lightly doped well;

removing said first mask from said silicon body;

forming an insulated gate structure over said silicon body;

opening a second window that extends at least partially through said insulated gate structure over said dopant-introduction site and adjacent material of said silicon body;

forming a lightly doped region of the second conductivity type through said second window, said lightly doped region extending laterally beyond said lightly doped well and said heavily doped region and under said insulated gate structure;

masking a portion of said heavily doped region within said second window to form a third window; and

forming a heavily doped region of said first conductivity type aligned with said third window.

16. A method as in claim 15 wherein:

said second conductivity type is P type; and

said heavily doped region of the second conductivity type forms a junction depth shallower than 2.5 microns.

17. A method as in claim 16 wherein said lightly doped well has a depth at least 0.5 micron deeper than said junction depth.

18. A method as in claim 15, wherein said step of forming said heavily doped region comprises the steps of:

forming a glass rich in a dopant of said second conductivity type on said silicon body in said first window; and

diffusing dopant from said dopant rich glass into said lightly doped well.

19. A method as in claim 15, wherein all interior angles of said second window are not less than about 120 degrees.

20. A method comprising the steps of:

forming a structure in which (a) a gate insulating layer overlies active and termination areas of a monocrystalline semiconductor body, (b) a gate polycrystalline semiconductor portion lies over said insulating layer largely above the active area, (c) a peripheral polycrystalline semiconductor portion lies over said insulating layer, is laterally separated from said gate polycrystalline portion, and laterally extends above a scribe line part of the termination area, (d) a gate electrode contacts said gate polycrystalline portion, and (e) a source electrode contacts the active area through openings in said insulating layer; and

scribing said peripheral polycrystalline portion over the termination area.

21. A method as in claim 20 wherein said peripheral polycrystalline portion substantially laterally surrounds said gate polycrystalline portion.

22. A method as in claim 21 wherein said structure further includes a plurality of source regions situated in the active area.