Method of forming a mask programmable read only memory device with multi-level memory cell array

• US 5,429,968 A
• Filed: 09/14/1994
• Issued: 07/04/1995
• Est. Priority Date: 07/12/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Koyama, Shoji
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/305,745
• Time in Patent Office: 293 Days
• Field of Search: 437/44, 437/47-48, 437/52, 437/101, 437/45, 257/290-292
• US Class Current: 438/152
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 17/123 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A mask programmable read only memory device comprises a plurality of memory cell blocks each having a plurality of first series combinations of memory transistors and a plurality of second series combinations of memory transistors, and each of the memory transistors is operative in either enhancement or depletion mode, wherein the plurality of first series combinations are respectively overlapped with the plurality of second series combinations so as to share word lines therebetween, thereby increasing the integration density without sacrifice of the real estate.

Claims

1. A process of fabricating a mask programmable read only memory device on a semiconductor substrate of a first conductivity type, comprising the steps of:

a) preparing said semiconductor substrate;

b) selectively growing a first gate insulating film over a major surface of said semiconductor substrate;

c) forming a plurality of first gate electrodes on said first gate insulating film at spacings;

d) forming first source and drain regions of a second conductivity type in said semiconductor substrate in such a manner that said first gate insulating film, said plurality of first gate electrodes and said first source and drain regions are connected in series combination to form enhancement mode first field effect transistors;

e) covering said plurality of first gate electrodes with a second gate insulating film;

f) forming a semiconductor film of said first conductivity type on said second gage insulating film in such a manner as to extend over said plurality of first gate electrodes;

g) providing a first mask film on said semiconductor film having through holes exposing parts of said semiconductor film over a first set of gate electrodes selected from said plurality of first gate electrodes;

then

h) implanting impurities of said second conductivity type at relatively large acceleration energy, and doping said semiconductor substrate under said first gate electrodes so as to selectively convert said enhancement mode first field effect transistors into depletion mode first field effect transistors;

i) removing said first mask film;

j) providing a second mask film on said semiconductor film having through holes covering parts of said semiconductor film over a second set of gate electrodes selected from said plurality of first gate electrodes;

k) implanting impurities of said second conductivity type into said semiconductor film at relatively small acceleration energy, and doping said semiconductor film except for said parts, the gate electrodes under said parts,

wherein said second gate insulating film and said parts are connected in combination to form enhancement mode second field effect transistors, and the other of said gate electrodes, said second gate insulating film and said semiconductor film except for said parts are connected in combination to form depletion mode second field effect transistors,

said depletion mode second field effect transistors and said enhancement mode second field effect transistors being mixed for forming a series combination of second field effect transistors; and

l) completing said mask programmable read only memory device.

2. A process as set forth in claim 1, in which said step j) comprises the substeps of:

j-1) depositing an oxide film over the entire surface, j-2) patterning a photo resist film for forming said second mask film, and j-3) patterning said oxide film for exposing said semiconductor film.

3. A process as set forth in claim 1, in which said step l) comprises the substeps of:

l-1) removing said second mask film, l-2) depositing a refractory metal film over said oxide film left on said semiconductor film as well as over exposed semiconductor film, and l-3) applying heat to said semiconductor film overlain by said refractory metal film so as to form a refractory metal silicide film.