Method of implanting during manufacture of ROM device

• US 5,429,975 A
• Filed: 10/25/1993
• Issued: 07/04/1995
• Est. Priority Date: 10/25/1993
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsue, Chen-Chiu, Chung, Chen-Hui, Sheu, Shing-Ren
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/140,401
• Time in Patent Office: 617 Days
• Field of Search: 437/52, 437/47, 437/48
• US Class Current: 438/276
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/383 Channel doping programmed

Abstract

A ROM device with an array of cells and a method of manufacturing comprises: forming closely spaced conductors in the surface of a semiconductor substrate having a second type of background impurity. Insulation is formed on the substrate. Closely spaced, parallel, conductors on the insulation are arranged orthogonally to the line regions. Glass insulation is formed over the conductors. Reflowing the glass insulation, forming contacts and forming a metal layer on the glass insulation follow. A resist is formed, exposed forming a resist metal pattern, then etching through the resist to pattern metal and removing the resist. Depositing a resist onto the patterned metal, and exposing the second resist with a custom code pattern, developing the resist into a mask follow. Impurity ions are implanted into the substrate adjacent to the conductors through the openings in a second resist layer. The device is passivated followed by activating the implanted impurity ions by annealing the device at a temperature less than or equal to about 520° C. in a forming gas or N₂ atmosphere.

Claims

1. An improved method of manufacturing a Read Only Memory device with an array of cells comprising:

a) forming a plurality of spaced line regions with a first P or N impurity type in and adjacent to the surface of a semiconductor substrate having a background impurity type,

b) forming an insulating layer on the surface of said substrate,

c) forming a plurality of spaced, parallel, electrically conductive word lines on said insulating layer arranged orthogonally relative to said line regions,

d) forming a glass insulating layer comprising an undopad glass sublayer having a thickness of about 1,000 Å

over said conductive lines, followed by forming a of doped glass overlayer over said undopad glass sublayer, said overlayer having a thickness between about 1,000 Å and

about 2,000 Å

,

e) reflowing said glass insulating layer at a temperature of about 900°

C. to planarize said glass sublayer and said glass overlayer reducing the thickness of said overlayer with said overlayer and said sublayer having a combined thickness of about 2500 Å

over said word lines,

f) forming contacts,

g) forming a metal layer and a titanium nitride layer on said glass insulating layer,

h) depositing a resist layer on said metal layer,

i) exposing said resist layer with a metal pattern, etching said metal layer and said glass overlayer through said resist layer to form patterned metal leaving behind said glass underlayer with a range of thickness of said glass underlayer with a thickness between about 500 Å and

about 1,500 Å and

then removing said resist layer,

j) depositing a second resist layer onto said device, and exposing said second resist layer with an ion implantation pattern,

k) developing said second resist layer into a mask,

l) implanting impurity ions into said substrate adjacent to said conductive lines through said openings in said second mask,

m) removing said second resist layer,

n) passivating said device, and

o) activating said implanted impurity ions by annealing said device at a temperature between about 400°

C. and about 520°

C. in a gas atmosphere,

whereby the metallurgy and the electrical contacts to the substrate, line regions and conductor lines are protected from adverse effect during annealing.

2. A method in accordance with claim 1 wherein said doped glass overlayer comprises BPSG or BPTEOS.

3. A method in accordance with claim 1 wherein said doped glass overlayer comprises glass doped with boron and phosphorous.

4. A method in accordance with claim 1 wherein said doped glass overlayer comprises glass doped with boron between about 2.5 weight percent and about 5 weight percent and a concentration of phosphorous between about 3 weight percent and about 5.5 weight percent.

5. A method in accordance with claim 1 wherein said doped glass overlayer comprises glass doped with about 3.0 weight percent boron and 5.2 weight percent phosphorous.

6. A method in accordance with claim 1 wherein said metallization comprises a layer of aluminum having a thickness between about 8,000 Å

and about 11,000 Å

, and a thin upper layer of titanium nitride having a thickness between about 100 Å and

about 400 Å

.

7. A method in accordance with claim 6 wherein said aluminum is about 10,000 Å

thick and said layer of titanium nitride is about 300 Å

thick.

8. A method in accordance with claim 4 wherein said metallization comprises a layer of aluminum having a thickness between about 8,000 Å

and about 11,000 Å

, and a thin upper layer of titanium nitride having a thickness within the range from about 100 Å

to about 400 Å

.

9. A method in accordance with claim 4 wherein said aluminum is about 10,000 Å

thick and said layer of titanium nitride is about 300 Å

thick.

10. A method in accordance with claim 5 wherein said aluminum is about 10,000 Å

thick and said layer of titanium nitride is about 300 Å

thick.

11. A method in accordance with claim 1 wherein said gas atmosphere comprises N₂ alone or in combination with H₂.