Method for forming a vertical transistor with a stacked capacitor DRAM cell

• US 5,429,977 A
• Filed: 03/11/1994
• Issued: 07/04/1995
• Est. Priority Date: 03/11/1994
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Tseng, Horng-Huei, Lu, Chin-Yuan
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/208,713
• Time in Patent Office: 480 Days
• Field of Search: 437/47, 437/52, 437/60, 437/919, 257/301-303, 257/306, 257/309
• US Class Current: 438/242
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.

Claims

1. The method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising:

providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate and a pattern of bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which said lines cross at the locations of said vertical DRAM cell at said pattern of openings to the silicon substrate;

said bit lines are source/drain elements surrounding said hole in the surface of said substrate and source/drain elements located at the bottom of said hole are formed simultaneously by ion implantation using the field oxide as the mask;

forming a gate dielectric on the surfaces of said holes;

forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric and said field oxide isolation;

forming a silicon nitride layer over said doped polysilicon layer;

patterning and etching said silicon nitride layer and doped polysilicon layer to form a opening for a capacitor node contact to said bit line source/drain and establish said gate electrode in said hole and word line pattern over the said field oxide insulator;

forming a silicon oxide spacer over the sidewalls of said silicon nitride and said doped polysilicon layer to complete said vertical transistor;

forming a capacitor node polysilicon electrode in said hole and in node contact to said source/drain elements at the bottom of said hole;

forming a capacitor dielectric over said capacitor node polysilicon electrode; and

forming a capacitor polysilicon plate electrode over said capacitor dielectric to complete said vertical DRAM cell.

2. The method of claim 1 wherein the dopant concentration level of said buried source/drain lines is between about 2 E 15 to 1 E 16 atoms/cm³.

3. The method of claim 1 wherein the size of said pattern of openings to said silicon substrate is between about 8000 to 12000 Angstroms.

4. The method of claim 1 wherein said hole located within each of said openings to said silicon substrate is centrally located therein, the hole reaches to said buried source/drain elements, and has a diameter of between about 2000 to 4000 Angstroms.

5. The method of claim 4 wherein the depth of said hole is between about 4000 to 10000 Angstroms.

6. The method of claim 1 wherein said source/drain elements surrounding said gate electrode in the surface of said substrate and said bit lines/source/drain elements are the bottom of the said hole cooperate with said gate electrode to form said field effect transistor of said vertical channel DRAM cell.

7. The method of claim 6 wherein said capacitor is connected to said field effect transistor to form said vertical DRAM cell and the capacitor is physically directly over the field effect transistor and with its node contact to said source/drain elements at the bottom of said hole.

8. The method for fabricating a vertical DRAM cell which includes a vertical channel field effect transistor having a gate electrode and source/drain elements and a capacitor comprising:

providing a silicon substrate;

forming a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate;

forming a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and locations of bit lines of said vertical DRAM cell at said pattern of openings to the silicon substrate;

simultaneously forming said source/drain elements surrounding said hole in the surface of said substrate and said source/drain elements at the bottom of said hole by ion implantation using the field oxide as the mask;

wherein said source/drain elements surrounding said hole are bit lines for said cell;

forming a gate dielectric on the surfaces of said holes;

forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric and said field oxide isolation;

forming a silicon nitride layer over said doped polysilicon layer;

patterning and etching said silicon nitride layer and doped polysilicon layer to form a opening for a capacitor node contact to said source/drain elements at the bottom of said hole and to establish said gate electrode in said hole and word line pattern over the said field oxide insulator;

forming a silicon oxide spacer over sidewalls of said silicon nitride and said doped polysilicon layer;

forming a capacitor node polysilicon electrode in said hole and in node contact to said source/drain elements;

forming a capacitor dielectric over said capacitor node polysilicon electrode; and

forming a capacitor polysilicon plate electrode over said capacitor dielectric to complete said vertical DRAM cell.

9. The method of claim 8 wherein the dopant concentration level of said buried source/drain lines is between about 2 E 15 to 1 E 16 atoms/cm³.

10. The method of claim 8 wherein the size of said pattern of openings to said silicon substrate is between about 8000 to 12000 Angstroms.

11. The method of claim 8 wherein said hole located within each of said openings to said silicon substrate is centrally located therein, the hole reaches to said buried source/drain elements, and has a diameter of between about 2000 to 4000 Angstroms.

12. The method of claim 11 wherein the depth of said hole is between about 4000 to 10000 Angstroms.

13. The method of claim 8 wherein said source/drain elements surrounding said gate electrode in the surface of said substrate and said bit lines source/drain elements are the bottom of the said hole cooperate with said gate electrode to form said field effect transistor of said vertical channel DRAM cell.

14. The method of claim 13 wherein said capacitor is connected to said field effect transistor to form said vertical DRAM cell and the capacitor is physically directly over the field effect transistor and with its node contact to said source/drain elements at the bottom of said hole.