Method of making linear capacitors for high temperature applications

• US 5,429,981 A
• Filed: 06/30/1994
• Issued: 07/04/1995
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Gardner, Gary R., Liu, Michael S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/269,265
• Time in Patent Office: 369 Days
• Field of Search: 437/60, 437/21, 437/919, 437/62, 437/67, 437/238, 437/979
• US Class Current: 438/394
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A method for making a voltage linear capacitor for use with a metal oxide semiconductor field transistor wherein a capacitor portion of an SOI substrate is heavily doped with phosphorus. The thin oxide layer used for the transistor gate oxide also serves as the capacitor dielectric and the thickness of the dielectric relative to the gate oxide is controlled.

Claims

1. A method for making a capacitor for use with a metal oxide semiconductor field effect transistor, comprising the steps of:

providing a silicon on insulator substrate having a first region for use as a first plate of said capacitor and a second region for forming said transistor;

isolating said first region;

implanting phosphorus ions into said first region to provide a first concentration of said phosphorus ions within said first region;

forming an oxide layer over said first and second regions with said oxide layer over said first region having a first thickness and said oxide layer over said second region having a second thickness, with said first thickness exceeding said second thickness by not more than 30 percent;

depositing a polysilicon over said first and second regions layer; and

removing a portion of said polysilicon layer and of said oxide layer to define a gate for said transistor and to define a dielectric and a second plate of said capacitor.

2. Method of claim 1 wherein said step of implanting phosphorus ions comprises the following steps:

forming a barrier oxide on said substrate;

masking said barrier oxide to allow implantation through said barrier oxide only in said isolated first region; and

removing said barrier oxide.

3. Method of claim 2 wherein said barrier oxide has a thickness of about 2000 angstroms and said phosphorus ions are implanted at a dose of about 6E14 per cm² and an ion energy of about 190 KeV.

4. Method of claim 1 wherein said oxide layer over said second region has a thickness of 150 to 400 angstroms.

5. Method of claim 1 wherein said step of implanting phosphorus ions comprises the following steps:

forming a pad oxide on said substrate;

masking said pad oxide to allow implantation through said pad oxide only in said isolated first region; and

removing said pad oxide.

6. Method of claim 5 wherein said pad oxide has a thickness of about 200 angstroms and said phosphorus ions are implanted at a dose of about 0.6E15 and an ion energy of about 30 Kev.

7. A method for making a capacitor for use with a metal oxide semiconductor field effect transistor, comprising the steps of:

providing a silicon on insulator substrate having a first region for use as a first plate of said capacitor and a second region for forming said transistor;

isolating said first region;

implanting impurity ions into said first region to provide a first concentration of said impurity ions within said first region;

forming by growth an oxide layer over said first and second regions with said oxide layer over said first region having a first thickness and said oxide layer over said second region having a second thickness, with said first thickness exceeding said second thickness by less than 30 percent of said second thickness;

depositing a polysilicon layer over said first and second regions; and

removing portions of said polysilicon layer and of said oxide layer to define a gate for said transistor and to define a dielectric and a second plate of said capacitor.

8. Method of claim 7 wherein said impurity ions are selected from the group consisting of phosphorus and arsenic.

9. Method of claim 8 wherein said step of implanting includes implanting phosphorus ions at a dose of about 6E14 per cm² and an energy of about 190 KeV through a barrier oxide having a thickness of about 2000 angstroms.

10. Method of claim 9 wherein said step of implanting includes implanting phosphorus ions at a dose of about 6E14 per cm² and an energy of about 60 KeV through a pad oxide having a thickness of about 200 angstroms.

11. A method for making a capacitor for use with a metal oxide semiconductor field effect transistor, comprising the steps of:

providing a silicon on insulator substrate having a first region for use as a first plate of said capacitor and a second region for forming said transistor;

isolating said first region;

forming a first oxide layer on said substrate;

implanting phosphorus ions through said first oxide layer into said first region to provide a first concentration of said phosphorus ions within said first region;

removing said first oxide layer;

forming a second oxide layer over said first and second regions with said second oxide layer over said first region having a first thickness and said second oxide layer over said second region having a second thickness, with said first thickness exceeding said second thickness by not more than 30 percent;

depositing a polysilicon over said first and second regions layer; and

removing a portion of said polysilicon layer and of said second oxide layer to define a gate for said transistor and to define a dielectric and a second plate of said capacitor.