Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current

• US 5,430,315 A
• Filed: 10/11/1994
• Issued: 07/04/1995
• Est. Priority Date: 07/22/1993
• Status: Expired due to Fees

• Current Assignee: Vladimir Rumennik
• Original Assignee: Vladimir Rumennik
• Inventors: Rumennik, Vladimir
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/321,579
• Time in Patent Office: 266 Days
• Field of Search: 257/330, 257/331, 257/332, 257/333, 257/334, 257/341, 257/342, 257/401, 257/402, 257/403
• US Class Current: 257/331
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trench MOSFET that includes a charge carrier getter region to substantially deplete a plurality of body regions during an off-state of this MOSFET to produce a very low off-state leakage current. In a first class of embodiments, this charge carrier getter region is a thin layer of material, of opposite conductivity type to that of the body regions, and located between a plurality of gate regions and the body regions. In a second class of embodiments, the gate regions are of opposite conductivity type to the body regions to function as a charge carrier getter region as well as a gate region.

Claims

1. A trench MOSFET comprising:

(a) at least one pedestal, that functions as a vertically-oriented body region, doped with a first conductivity type of dopant, extending in a direction from a top surface to a bottom surface of this MOSFET;

(b) for each of said pedestals;

(b.1) at least one gate region adjacent to a sidewall of said pedestal and extending across substantially the entire sidewall to control conduction of current throughout said pedestal, whereby a voltage applied to said gate region controls a conductivity of said pedestal;

(b.2) an insulating layer, on a sidewall of said pedestal, between said gate region and said pedestal; and

(b.3) at least one charge carrier getter region, of a second conductivity type opposite to the first conductivity type, in electrical contact with said pedestal, whereby, between each pedestal and each charge carrier getter region with which it is in electrical contact, is formed a p-n junction that tends to deplete a charge carrier density within said pedestal;

wherein a dopant concentration in each charge carrier getter region, a dopant concentration of each body region, a width of each charge carrier getter region, a width of each body region, a thickness of each charge carrier getter region and a thickness of each body region are selected to substantially deplete each body region when said trench MOSFET is in an off-state.

2. A trench MOSFET as in claim 1 further comprising:

means for varying a bias applied to said gate to control whether this MOSFET is in an off-state or an on-state.

3. A trench MOSFET as in claim 1, wherein said charge carrier getter region is located between said gate region and said at least one body region.

4. A trench MOSFET as in claim 1 wherein said charge carrier getter region has a thickness T₁₁₂ substantially equal to a thickness T₁₄ of said body regions, whereby said charge carrier getter region extends across substantially all of a sidewall of said body region, located between said body region and said gate region.

5. A trench MOSFET as in claim 1 wherein a dopant concentration C₁₁₂ in the charge carrier getter region, a width W₁₁₂ of the charge carrier getter region, a width W₁₄ of the body regions, a thickness T₁₁₂ of the charge carrier getter regions and a thickness T₁₄ of the body regions are selected to substantially deplete both said body regions and said getter regions when said trench MOSFET is in an off-state.

6. A trench MOSFET as in claim 1 wherein said gate region and said charge carrier getter region are the same region and are of a second conductivity type opposite to the first conductivity type.

7. A trench MOSFET as in claim 1 wherein said charge carrier getter region has a thickness T₁₅ equal to or greater than the thickness T₁₄ of said body regions and extends across all of a sidewall of said body region, whereby current carried along a conductive channel, formed at each sidewall of a body region, will emerge from the conductive channel into a middle layer of higher conductivity than the body region.

8. A trench MOSFET as in claim 1 further comprising a middle substrate layer in contact with a bottom surface of each body region and having a conductivity selected to control a breakdown voltage of the trench MOSFET.

9. A trench MOSFET as in claim 1 wherein said gate region comprises a conductive material that fills an interconnected plurality of trenches that interlink to form said pedestals.

10. A trench MOSFET comprising:

(a) at least one pedestal, that functions as a vertically-oriented body region extending in a direction from a top surface to a bottom surface of this trench MOSFET, doped with a first conductivity type of dopant;

(b) for each of said at least one pedestal;

(b.1) an insulating layer on a sidewall of each of said at least one pedestal; and

(b.2) at least one gate region, of opposite conductivity type to that of each of said at least one pedestal, in contact with the insulating layer on a sidewall of each of said at least one pedestal, to control a conductivity of each of said at least one pedestal, the composition and doping of said gate region and said pedestals being selected such that this pedestal is substantially depleted of charge carriers in an off-state of this trench MOSFET;