Field effect transistor with switchable body to source connection
First Claim
1. A circuit comprising:
- a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region, wherein said second region is connected to a first voltage and said first region is connected to an output terminal of said circuit; and
a second transistor connected between said first region and said body region of said first FET,a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive.
1 Assignment
0 Petitions
Accused Products
Abstract
To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.
46 Citations
18 Claims
-
1. A circuit comprising:
-
a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region, wherein said second region is connected to a first voltage and said first region is connected to an output terminal of said circuit; and a second transistor connected between said first region and said body region of said first FET, a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A circuit comprising:
-
a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region; a second transistor connected between said first region and said body region of said first FET, a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive; and a third transistor connected between said body region of said first FET and a reference voltage, said third transistor having a control terminal coupled to said gate of said first FET such that said third transistor is made conductive only when said first FET is non-conductive. - View Dependent Claims (8, 9)
-
-
10. A circuit comprising:
-
a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region; and a second transistor connected between said first region and said body region of said first FET, a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive, wherein an output terminal of said circuit is connected to said first region, and said second region is connected to a first supply voltage, said output terminal having applied to it a voltage higher than said first supply voltage when said first FET is in a non-conductive state. - View Dependent Claims (11, 12, 13)
-
-
14. A circuit comprising:
-
a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region; and a second transistor connected between said first region and said body region of said first FET, a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive, wherein said first region and said second region are formed in said body region of said second conductivity type, said body region formed within a semiconductor material of said first conductivity type, said second transistor comprising a double-diffused MOS transistor having a third region of said first conductivity type formed in said body region, a portion of said body region forming a channel for said second transistor. - View Dependent Claims (15, 16, 17)
-
-
18. A circuit comprising:
-
a first field effect transistor (FET) having a first region of a first conductivity type, a second region of said first conductivity type, a body region of a second conductivity type between said first region and said second region, and a gate formed overlying said body region beween said first region and said second region; a second transistor connected between said first region and said body region of said first FET, a control terminal of said second transistor being connected to said gate of said first FET such that said first FET and said second transistor are simultaneously conductive or non-conductive; a second FET substantially identical to said first FET, said second FET having a first region of said first conductivity type, a second region of said first conductivity type, a body region of said second conductivity type between said first region and said second region, and a gate formed overlying said body region between said first region and said second region; and a third transistor substantially identical to said second transistor, said third transistor being connected between said first region and said body region of said second FET, a control terminal of said third transistor being connected to said gate of said second FET such that said second FET and said third transistor are simultaneously conductive or non-conductive, said first region of said second FET being connected to said first region of said first FET, said second region of said second FET being connected to a voltage which is different from a voltage connected to said seccond region of said first FET for forming a voltage multiplexer.
-
Specification