Method and apparatus for sequential programming of a flash EEPROM memory array

• US 5,430,674 A
• Filed: 06/02/1994
• Issued: 07/04/1995
• Est. Priority Date: 09/10/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Javanifard, Johnny
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/252,850
• Time in Patent Office: 397 Days
• Field of Search: 365/218, 365/185, 365/900, 365/189.04, 365/189.09, 365/220, 365/227, 365/189.01
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

An integrated circuit arrangement for providing programming voltages to a flash EEPROM memory array including an arrangement for selecting only bits of a word which are to be programmed and applying programming voltages only to the memory transistors of a selected subset of those bits to be programmed until all bits to be programmed in a word have been programmed.

Claims

1. A computer system comprising:

a central processor;

a memory arrangement that further comprises

a flash EEPROM memory array including a plurality of floating gate field effect transistor devices,

a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation,

a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed,

control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and

a system bus for transferring data and addresses between the central processor and the memory arrangement.

2. A computer system as claimed in claim 1 in which the control circuitry is a processor which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

3. A computer system as claimed in claim 1 in which the selected number is four.

4. A computer system as claimed in claim 1 in which the control circuitry is an application specific logic circuit which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until yhe data word has been programmed.

5. A memory arrangement comprising:

a flash EEPROM memory array including a plurality of floating gate field effect transistor devices,

a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation,

a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and

control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

6. A memory arrangement as claimed in claim 5 in which the control circuitry is a processor which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

7. A memory arrangement as claimed in claim 5 in which the selected number is four.

8. A memory arrangement as claimed in claim 5 in which the control circuitry is an application specific logic circuit which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

9. A computer system comprising:

central processing means;

means for providing storage of data, further comprising

flash EEPROM memory array means including a plurality of floating gate field effect transistor devices,

charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation,

means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed,

control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and

system bus means for transferring data and addresses between the central processing means and the means for providing storage for data.

10. A computer system as claimed in claim 9 in which the control means includes processor means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

11. A computer system as claimed in claim 9 in which the selected number is four.

12. A computer system as claimed in claim 9 in which the control means includes application specific logic means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

13. An arrangement for providing storage of data comprising:

flash EEPROM memory array means including a plurality of floating gate field effect transistor devices,

charge pump means for providing a voltage to be applied to terminals of the floating gate field effect transistor devices during a programming operation,

means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and

control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

14. An arrangement for providing storage of data as claimed in claim 13 in which the control means includes processor means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

15. An arrangement for providing storage of data as claimed in claim 13 in which the selected number is four.

16. An arrangement for providing storage of data as claimed in claim 13 in which the control means includes application specific logic means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

17. A method for programming a flash EEPROM memory array including a plurality of floating gate field effect transistor devices comprising the steps of:

providing a first positive voltage,

comparing each bit of a data word to be programmed with a predetermined voltage to determine which bits of the data word are to be programmed,

enabling a selected group of bitlines in response to results of comparing to transfer the first positive voltage to a selected number of the plurality of floating gate field effect transistor devices coupled to the selected group of bitlines for programming, and

repeating each of the foregoing steps until all bits of the data word have been programmed.

18. A method as claimed in claim 17 which includes, after the step of enabling, the further step of determining whether additional bits exist in the word which are to be programmed but have not yet been programmed.

19. A method as claimed in claim 17 which includes the further step of verifying that all bits of a selected word have been programmed.