Burst mode digital data receiver

• US 5,430,766 A
• Filed: 08/22/1994
• Issued: 07/04/1995
• Est. Priority Date: 11/13/1992
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Ota, Yusuke, Swartz, Robert G.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): MAY, TIMOTHY
• Application Number:
  US08/293,908
• Time in Patent Office: 316 Days
• Field of Search: 375/76, 375/98, 307/268, 307/357, 307/358, 307/359, 455/239.1, 455/240.1, 328/149, 330/11
• US Class Current: 375/318
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/695 Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

A dc-coupled packet mode digital data receiver, for use with an optical bus uses peak detectors to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A dc compensator, responsive to outputs of the peak detectors, shunts dc or low frequency currents, corresponding to "dark level" optical signals, from the input of the receiver.

Claims

1. A digital data receiver comprising

a dc-coupled differential input amplifier circuit having first input means for receiving a digital data input signal, second input means for receiving a first reference signal, and differential output means for outputting a positive and a negative data output signals;

first detector means for detecting a first polarity peak amplitude of said positive data output signal and for generating said first reference signal;

second detector means for detecting a second polarity peak amplitude of said negative data output signal and for generating a second reference signal, said first and second polarities being the same; and

proportional means, responsive to a difference of said first and second reference signals, for continuously subtracting a proportional amount of a low frequency current of said data input signal from said first input means.

2. The receiver of claim 1 wherein said first detector means includes

means for storing said first polarity peak amplitude of said data output signal and

amplifier means for controlling a discharge rate of said means for storing.

3. The receiver of claim 2 wherein said detector means includes a slew booster amplifier for a charging of said storing means, said slew booster amplifier including a comparator means for enabling said slew booster amplifier when said data output signal exceeds said first reference signal by more than a predetermined offset voltage.

4. The receiver of claim 3 wherein said first detector means includes

detector output means having a resistor connected to said storing means and wherein a time constant formed by a product of said resistor value and said storing means value is a dominant pole in a feedback path between said output means and said second input means of said input amplifier circuit.

6. The receiver of claim 1 wherein said first and second detector means are each implemented using circuit apparatus having identical operating characteristics.

7. The receiver of claim 1 wherein said first and second detectors are part of an integrated circuit.

8. The receiver of claim 1 wherein said proportional means includes

comparison amplifier means having a first input connected to said first reference signal, a second input connected to said second reference signal, and an output means for controlling the continuous subtracting of a proportional amount of said low frequency current from said data input signal.

9. The receiver of claim 1 wherein said input amplifier circuit has a first feedback loop to regulate a magnitude of an input current to voltage output transfer characteristic of said input amplifier circuit.

10. The receiver of claim 1 wherein said digital data input signal is a current signal and wherein said input amplifier circuit is a transimpedance amplifier circuit.

11. The receiver of claim 1 wherein said digital data input signal is a voltage signal and wherein said input amplifier circuit is a voltage amplifier circuit.

12. The receiver of claim 1 wherein said first reference signal is a dc voltage approximately equal to one-half of a peak-to-peak amplitude of said positive data output signal.

13. The receiver of claim 1 wherein

said first detector means includes a differential input amplifier having a positive input means connected to said positive data output signal and having a negative input means connected to said first reference signal, and

said second detector means includes a differential input amplifier having a positive input means connected to said negative data output signal and having a negative input means connected to said second reference signal.

14. The receiver of claim 1 further including

converter means for converting a received optical input signal into said data input signal.

5. The receiver of claim I wherein said second detector means includes

means for storing said second polarity peak amplitude of said data output signal and

amplifier means for controlling the discharge rate of said means for storing.

15. A digital data receiver comprising

a dc-coupled differential amplifier circuit having first input means for receiving a digital data input signal, second input means for receiving a reference signal, and differential output means for outputting a first and second polarity data output signals;

first detector means for detecting a peak amplitude of said first polarity data output signal and for generating said reference signal; and

second detector means for detecting a difference between a first and second peak amplitudes of said first and second polarity data output signals, respectively, said first and second peak amplitudes being of the same polarity, and in response thereto continuously subtracting a proportional amount of a low frequency current from said data input signal at said first input means.

16. A digital data receiver comprising

a dc-coupled differential amplifier circuit having first input means for receiving a digital data input signal, second input means for receiving a reference signal, first output means for outputting a first data output signal and a second output means for outputting a second data output signal;

first detector means for detecting a first polarity peak amplitude of said first data output signal and for generating said reference signal;

second detector means for detecting a second polarity peak amplitude of said second data output signal, said first and second polarity being the same; and

means, responsive to a difference signal from said first and second detector means, for continuously subtracting a portion of said data input signal from said first input means.

17. A digital data receiver comprising

a dc-coupled amplifier circuit having first input means for receiving a digital data input signal, having a dc current component, second input means for receiving a first reference signal, and in response thereto generating a positive and negative data output signals;

first detector means for detecting a first peak amplitude of said first data output signal and for generating said first reference signal; and

second detector means for detecting a difference between a first polarity peak amplitude of said positive data output signal and said first polarity peak amplitude of said negative data output signal and for generating a second dc current which is continuously subtracted from said dc current component of said data input signal.

18. An optical signal receiver comprising

means for receiving a digital optical signal,

means for converting the received digital optical signal into an electronic data signal,

a dc-coupled differential input amplifier circuit having first input means for receiving said electronic data signal, second input means for receiving a first reference signal, and differential output means for outputting first and second data output signals;

first detector means for detecting a first peak amplitude of said first data output signal and for generating said first reference signal; and

second detector means for detecting a difference between a first polarity peak amplitude of said first data output signal and said first polarity peak amplitude of said second data output signal and in response thereto continuously subtracting a proportional amount of a low frequency current from said data input signal at said first input means.