Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching

• US 5,430,854 A
• Filed: 10/27/1993
• Issued: 07/04/1995
• Est. Priority Date: 10/24/1991
• Status: Expired due to Term

• Current Assignee: Allen H. Simon, Anthony P. Bertapelli, David L. Sprague, Eiichi Kowashi, George F. Salem, Kevin Harney, Michael Keith, Michael Papadopoulos, Shih-Wei Shiue, Vitaly H. Shilman, Walter P. Hays
• Original Assignee: Allen H. Simon, Anthony P. Bertapelli, David L. Sprague, Eiichi Kowashi, George F. Salem, Kevin Harney, Michael Keith, Michael Papadopoulos, Shih-Wei Shiue, Vitaly H. Shilman, Walter P. Hays
• Inventors: Kowashi, Eiichi, Keith, Michael, Papadopoulos, Michael, Simon, Allen H., Sprague, David L., Harney, Kevin, Salem, George F., Bertapelli, Anthony P., Hays, Walter P., Shilman, Vitaly H., Shiue, Shih-Wei
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ellis, Richard Lee
• Application Number:
  US08/144,219
• Time in Patent Office: 615 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/236
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.

Claims

1. A data processing system having executing means for executing instructions of an instruction sequence, said instructions having instruction cycles, comprising:

instruction means for applying instructions of said sequence of instructions to said executing means;

means for sequentially determining at least first and second conditionals in accordance with differing instructions of said applied instructions;

means for setting respective first and second conditional mask flags in accordance with said first and second determined conditionals;

means for simultaneously storing said first and second mask flags;

means for sequentially retrieving said first and second conditional mask flags in a predetermined order; and

,

said executing means having means for executing selected instructions of said applied instructions and idling during the instruction cycle of selected instructions of said applied instructions in accordance with said sequentially retrieved conditional mask flags, and

wherein there is provided external memory and a plurality of said executing means arranged as parallel datapaths for simultaneously executing an identical instruction of said instruction sequence, each executing means having at least one individual conditional mask flag and conditional mask flag setting means comprising;

means for determining a respective conditional mask flag of each of said executing means, including consensus means for determining that the respective conditional mask flags of all executing means of said plurality of executing means are in a single state; and

,

condition branching means, responsive to said consensus means, for implementing conditional branching to a new sequence of instructions when all of said respective conditional mask flags are in a single state.