Semiconductor memory device

• US 5,432,365 A
• Filed: 03/09/1993
• Issued: 07/11/1995
• Est. Priority Date: 02/15/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chang-Hyun, Chin, Dae-Je
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/038,842
• Time in Patent Office: 854 Days
• Field of Search: 357/23.6, 257/301, 257/304
• US Class Current: 257/301
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

There is disclosed a memory cell made with a semiconductor substrate for mounting integrated circuit elements, and having a trench for forming a capacitor region extending vertically to the surface of the substrate. In the substrate region around the trench is formed a cell plate region of second conductivity type for forming a charge storage region within the capacitor region. A high concentration semiconductor region of the same conductivity type as the substrate is formed in the substrate region outside the cell plate region to increase the charge stored in the capacitor region. A conducting material stores charge responding to the voltage given within the trench. A dielectric layer is formed between the conducting material and the cell plate.

Claims

1. In a dynamic random access memory device including a semiconductor substrate, a storage capacitor for storing charges in said semiconductor substrate, and a transfer transistor having gate, source and drain for transferring the charges to said storage capacitor, said memory device comprising:

trench means for forming a capacitor region extending vertically from the surface of and into said substrate, said trench means having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-walls being masked to prevent penetration of dopants;

first dopant means for forming one electrode of said capacitor region, said first dopant means comprising impurities doped into side-walls of said lower portion of said trench means;

second dopant means formed in the substrate outside and adjacent to said first dopant means, for increasing charge storage in said capacitor region, said second dopant means surrounding and isolating said first dopant means from the surface of said substrate, said first and second dopant means being spaced-apart from the surface of said substrate;

conducting means for storing a charge corresponding to a voltage given, said conducting means being formed in said trench means;

dielectric means formed between said trench means and said conducting means to serve as an insulator of said capacitor region; and

connecting means for connecting said conducting means with said transfer transistor to transfer the charge to said capacitor region.

2. A dynamic random access memory device as claimed in claim 1, further comprised of:

one of said source and said drain of said transfer transistor disposed into the surface of said substrate and separated by said dielectric means from said conducting means; and

said connecting means overlying and electrically coupling said one of said source and drain with said conducting means.

3. A dynamic random access memory device as claimed in claim 1, wherein said second dopant means is formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means for enabling an increase of charge storage in said capacitor region.

4. A dynamic random access memory device as claimed in claim 3, wherein said substrate is a first conductivity type, said first dopant means is a second conductivity type, and said second dopant means has the said conductivity type as said substrate.

5. A dynamic random access memory device as claimed in claim 4, wherein said first conductivity type is P-type, and said second conductivity type is N-type.

6. In a dynamic random access memory device comprising a plurality of dynamic random access memory cells having a semiconductor substrate, a storage capacitor for storing charges, and a transfer transistor having gate, source and drain for transferring the charges to said storage capacitor, said memory device comprising:

trench means for forming a capacitor region extending vertically from the surface of and into said substrate, said trench means having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-walls being masked to prevent penetration of dopants;

first dopant means for forming one electrode of said capacitor region, said first dopant means comprising impurities doped into side-walls of said lower portion of said trench means;

second dopant means formed in the substrate adjacent to and outside of said first dopant means, for increasing charge storage in said capacitor region, said second dopant means surrounding and isolating said first dopant means from the surface of said substrate, and both of said first and second dopant means being spaced-apart from the surface of said substrate;

conducting means for storing a charge corresponding to a voltage given, said conducting means being formed in said trench means;

dielectric means formed between said trench means and said conducting means to serve as an insulator of said capacitor region;

connecting means for connecting said conducting means with said transfer transistor to transfer the charge to said capacitor region; and

well means having the same conductivity type as said first dopant means connected with said first dopant means of a dynamic random access memory cell adjacent to one end of an array of said plurality of random access memory cells.

7. A dynamic random access memory as claimed in claim 6, further comprised of:

one of said source and said drain of said transfer transistor disposed into the surface of said substrate and separated by said dielectric means from said conducting means; and

said connecting means overlying and electrically coupling said one of said source and drain with said conducting means.

8. A dynamic random access memory as claimed in claim 6, wherein said second dopant means is formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means for enabling an increase of charge storage in said capacitor region.

9. A dynamic random access memory as claimed in claim 8, wherein said substrate is a first conductivity type, said first dopant means is a second conductivity type, and said second dopant means has the same conductivity type as said substrate.

10. A dynamic random access memory as claimed in claim 9, wherein said first conductivity type is a P-type, and said second conductivity type is a N-type.

11. A dynamic random access memory as claimed in claim 10, wherein a voltage of V_CC /2 is applied to said well means.

12. A dynamic random access memory device, comprising:

a semiconductor substrate;

transfer transistor means having a gate, source and drain, for transferring charges;

trench means for forming a capacitor region extending vertically from the surface of and into said substrate, said trench means having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-walls being masked to prevent penetration of dopants;

first dopant means for forming a first electrode for said capacitor region, said first dopant means comprising impurities doped into side-walls of said lower portion of said trench means;

second dopant means formed in the substrate outside of and adjacent to said first dopant means, for increasing charge storage in said capacitor region, said second dopant means surrounding and isolating said first dopant means from the surface of said substrate, and both said first and second dopant means being spaced-apart from the surface of said substrate;

storage means for storing a charge in response to a given voltage, said storage means being formed in said trench means;

dielectric means formed between said trench means and said storage means to serve as an insulator of said capacitor region; and

connecting means for connecting said storage means with said transfer transistor means.

13. A dynamic random access memory device as claimed in claim 12, wherein said second dopant means is formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means for enabling an increase of charge storage in said capacitor region.

14. A dynamic random access memory device as claimed in claim 13, wherein said substrate is a first conductivity type, said first dopant means is a second conductivity type, and said second dopant means has the same conductivity type as said substrate.

15. A dynamic random access memory device as claimed in claim 14, wherein said first conductivity type is a P-type, and said second conductivity type is a N-type.

16. A dynamic random access memory device and a transfer transistor having gate, source and drain regions for transferring electric charges to a storage capacitor, said memory device comprising:

trench means for forming a capacitor region extending vertically from the surface of a substrate into said substrate, said trench means having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-walls being masked to prevent penetration of dopants;

first dopant means for forming one electrode of said capacitor region, said first dopant means comprising impurities doped into side-walls of said lower portion of said trench means;

second dopant means disposed in the substrate outside of and adjacent to said first dopant, for increasing charge storage in said capacitor region, said second dopant means surrounding and isolating said first dopant means from the surface of said substrate, said first and second dopant means being spaced-apart from the surface of said substrate;

conducting means for storing a charge corresponding to a voltage given, said conducting means being formed in said trench means; and

dielectric means formed between said trench means and said conducting means to serve as an insulator of said capacitor region.

17. A dynamic random access memory as claimed in claim 16, wherein said second dopant means is formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means for enabling an increase of charge storage in said capacitor region.

18. A dynamic random access memory device as claimed in claim 17, wherein said substrate is a first conductivity type, said first dopant means is a second conductivity type, and said second dopant means has the same conductivity type as said substrate.

19. A dynamic random access memory device as claimed in claim 18, wherein said first conductivity is a P-type, and said second conductivity type is a N-type.

20. A semiconductor device, comprising:

a substrate of a material having a first type conductivity;

trench means for forming a capacitor region extending vertically from one surface of and into said substrate, said trench means having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-walls being masked to prevent penetration of dopants;

first dopant means of a second type conductivity, for forming one electrode of said capacitor region, formed in the substrate, into side-walls of said lower portion of said trench means;

second dopant means of said first type conductivity formed in the substrate outside of and adjacent to said first dopant means, for reducing leakage current, said second dopant means surrounding and isolating vertical portions of said first dopant means from the material of said substrate having said first type conductivity;

conducting means for storing a charge, formed within said trench means;

dielectric means for isolating said conducting means from said first dopant means, disposed between said conducting means and said first dopant means; and

means for connecting said conducting means to other regions of the semiconductor device.

21. The semiconductor device of claim 20, further comprised of:

said first dopant means adjoining said material of said substrate having said first type conductivity in a volume of said substrate positioned vertically beneath and separated from said one surface by said trench means.

22. The semiconductor device of claim 20, further comprised of:

said first and second dopant means being spaced-apart from said one surface; and

said first dopant means adjoining said material of said substrate having said first type conductivity in a volume of said substrate positioned vertically beneath and separated from said one surface by said trench means.

23. The semiconductor device of claim 20, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

24. The semiconductor device of claim 20, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

25. The semiconductor device of claim 21, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

26. The semiconductor device of claim 22, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means, said one of said source and drain region being spaced apart from said first and second dopant means; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

27. The semiconductor device of claim 20, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means;

said second dopant means separating said first dopant means from said one of said source and drain region; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

28. The semiconductor device of claim 22, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means;

said second dopant means separating said first dopant means from said one of said source and drain region; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

29. The semiconductor device of claim 21, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means from said conducting means;

said second dopant means separating said first dopant means from said one of said source and drain region; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

30. A semiconductor device, comprising:

a substrate of a material having a first type conductivity;

a plurality of trenches for forming a plurality of discrete capacitor regions arranged in an array with each of said trenches extending vertically from one surface of and into said substrate, each of said trenches having an upper portion, and a lower portion formed continuously below said upper portion, said lower portion being narrower than said upper portion, and said upper portion having side-wall being masked to prevent penetration of dopants;

first dopant means of a second type conductivity disposed in the substrate, into side-walls of said lower portion of each of said trenches, for forming a first electrode for each of said capacitor regions;

second dopant means of said first type conductivity formed in the substrate adjacent to and around outside surfaces of said first dopant means oriented vertically to said one surface of said substrate, for reducing leakage current, said second dopant means surrounding and isolating said vertically oriented surfaces of said first dopant means from said material of said substrate having said first type conductivity, said first and second dopant means being spaced-apart from said one surface of said substrate, and said first dopant means extending beneath said second dopant means and adjoining said material of said substrate having said first type conductivity in a volume of said substrate vertically beneath and separated from said one surface of said substrate by each of said trenches;

conducting means for storing a charge, disposed within each of said trenches, for forming a second electrode for each of said capacitor regions;

dielectric means for isolating said conducting means from said first dopant means within each of said trenches, disposed between said conducting means and said first dopant means; and

means for connecting said conducting means to other regions of the semiconductor device and for transferring charges between said capacitor regions.

31. The semiconductor device of claim 30, wherein said second dopant means is formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means for enabling an increase of charge storage in each of said capacitor regions.

32. The semiconductor device of claim 30, further comprised of:

one of a source and a drain region disposed into said one surface and separated by said dielectric means of one of said plurality of capacitor regions from said conducting means corresponding to the same one of said capacitor regions, said one of said source and drain region being spaced apart from said first and second dopant means; and

said connecting means overlying and electrically coupling said one of said source and drain region with said conducting means.

33. A semiconductor memory device, comprising:

a substrate of a first type conductivity;

a trench for forming a capacitor region extending from one surface of and into said substrate, said trench having an upper portion and a lower portion narrower than said upper portion;

first dopant means of a second type conductivity, for forming a first electrode of said capacitor region, formed in the substrate and around said lower portion of said trench;

second dopant means of said first type conductivity, for reducing leakage current, formed in the substrate, outside of, adjacent to, and substantially enclosing said first dopant means;

conducting means for storing a charge, disposed within said trench, for forming a second electrode of said capacitor region;

dielectric means disposed between said conducting means and said first dopant means, for isolating said conducting means from said first dopant means; and

means for connecting said conducting means to other regions of the semiconductor memory device.

34. The semiconductor memory device as claimed in claim 33, further comprised of:

said second dopant means surrounding and isolating said first dopant means from the surface of said substrate, said first and second dopant means being spaced-apart from the surface of said substrate.

35. A semiconductor memory device comprising a substrate, a storage capacitor for storing charges in said substrate, and a transfer transistor having a gate, source and drain regions for transferring the charges to said storage capacitor, said semiconductor memory device comprising:

a trench for forming said storage capacitor extending vertically from the surface of and into said substrate, said trench having an upper portion, and a lower portion narrower than said upper portion, said upper portion having sidewalls being masked to prevent penetration of dopants;

first dopant means for forming a first electrode of said storage capacitor, said first dopant means comprising impurities of a first conductivity type doped into sidewalls of said lower portion of said trench;

second dopant means for blocking leakage current and preventing crosstalk between said first dopant means and said source region of said transfer transistor, said second dopant means comprising impurities of a second conductivity type doped in the substrate, and formed outside of and adjacent to said first dopant means to substantially enclose said first dopant means and isolate said first dopant means from the surface of said substrate for enabling an increase of charge storage in said storage capacitor;

conducting means disposed within said trench, for forming a second electrode of said storage capacitor to store said charges corresponding to a given voltage transferred by said transfer transistor;

dielectric means formed on sidewalls of said trench means and disposed between said conducting means and said first dopant means, for serving as an insulator of said storage capacitor; and

connecting means for connecting said conducting means with said source region of said transfer transistor to transfer the charges to said storage capacitor.

36. The semiconductor memory device as claimed in claim 35, further comprises:

said source region being disposed into the surface of said substrate, separated by said dielectric means from said conducting means, and spaced apart from said first and second dopant means; and

said connecting means overlying and electrically coupling said source region with said conducting means.