High withstand voltage M I S field effect transistor and semiconductor integrated circuit

• US 5,432,370 A
• Filed: 10/07/1994
• Issued: 07/11/1995
• Est. Priority Date: 08/17/1992
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Tada, Gen, Fujishima, Naoto, Kitamura, Akio
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/319,774
• Time in Patent Office: 277 Days
• Field of Search: 257/335, 257/336, 257/337, 257/338, 257/339, 257/340, 257/343, 257/401, 257/409
• US Class Current: 257/339
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor integrated circuit device is provided in which a highly reliable and low cost intelligent power semiconductor is mounted on the same substrate as that of a control circuit having a logic element, such as a low withstand voltage CMOS etc., and high withstand voltage and high current output MIS field effect transistor. A high withstand voltage MOSFET is composed of a vertical MOS portion 25 formed in one side of a laterally widened well layer 2 and a drain portion formed in the other side thereof and a second base layer 4 is formed on the surface of the well layer 2. Accordingly, a depletion layer widened just under the MOS portion 25 and the second base layer 4 develops a JFET effect at OFF time thereby realizing a high withstand voltage and reliability is provided since the generation of hot carriers can be prevented by the second base layer 4.

Claims

1. A high withstand voltage MIS field effect transistor comprising a second conductivity type well region formed on a first conductivity type semiconductor substrate;

a MOS portion providing a pair of first conductivity type first base layers formed in an outer portion of the well region, second conductivity type source layers formed in the first base layers and a gate electrode disposed over the source layers through an insulating layer;

a drain portion providing a second conductivity type drain layer formed in an inner portion of said well region, a first conductivity type second base layer formed in said well region between said MOS portion and said drain portion; and

a field oxide film formed on the surface of said second base layer.

2. A high withstand voltage MIS field effect transistor according to claim 1, wherein an edge portion of said drain layer is connected to an edge portion of said well region and the drain portion includes structure that provides said drain layer with a high withstand voltage.

3. A high withstand voltage MIS field effect transistor according to either of claims 1 or 2, wherein a first conductivity type high concentration buried layer is formed under said drain layer.

4. A high withstand voltage MIS field effect transistor according to either of claims 1 or 2, wherein when a reverse bias voltage of approximately 30 V is applied to said source layer and said drain layer, said MOS portion is a high withstand voltage MOS portion in which a depletion layer is expanded from said pair of base layers to said well region.

5. A high withstand voltage MIS field effect transistor according to either of claims 1 or 2, wherein a source electrode connected to said source layer is a field plate type source electrode extended by approximately 5 micrometer or more onto the field oxide film on said second base layer;

and a drain electrode connected to said drain layer is a field plate type drain electrode extended by approximately 5 micrometer or more onto the field oxide film on said second base layer.

6. A high withstand voltage MIS field effect transistor according to either of claims 1 or 2, wherein the impurity concentration of said second base layer is lower than the impurity concentration of said first base layer.

7. A high withstand voltage MIS field effect transistor according to either of claims 1 or 2, wherein said second base layer and said source layer are substantially concentrically formed with respect to the center of said drain layer.

8. A high withstand voltage MIS field effect transistor according to claim 7, wherein said second base layer is structured to provide an area through which said well layer and said field oxide film contact each other.

21. A semiconductor integrated circuit device according to any one of claims 1 or 2 or 19, wherein said high withstand voltage MIS field effect transistor is formed on a substrate which includes at least one of a bipolar transistor capable of composing a logic circuit or a MIS field effect transistor.

22. A semiconductor integrated circuit device according to any one of claims 1 or 2 or 19, wherein said high withstand voltage MIS field effect transistor is formed on the same substrate as a first conductivity type MIS field effect transistor which is connected in at least one of a digital circuit and an analog circuit, and said well region and a second conductivity type well layer of the MIS field effect transistor are commonly formed.

9. A high withstand voltage MIS field effect transistor having a second conductivity type well region formed on a first conductivity type semiconductor substrate;

a MOS portion providing in an outer portion of the well region, a second conductivity type source layer formed in a base layer and a gate electrode disposed through an insulating gate film over the source layer and an area of said well region;

a drain portion providing a second conductivity type drain layer formed in an inner portion of said well region;

a first conductivity type offset region formed in said well region between said MOS portion and said drain portion; and

a conducting layer disposed through an insulating film over said offset region.

10. A high withstand voltage MIS field effect transistor according to claim 9, wherein said conductor layer is of polycrystalline silicon.

11. A high withstand voltage MIS field effect transistor according to claim 9 or 10, wherein at least one portion of said offset region is formed under said gate electrode.

12. A high withstand voltage MIS field effect transistor according to claim 9 or 10, wherein said offset region provides at least two or more offset island regions.

13. A high withstand voltage MIS field effect transistor according to claim 9 or 10, wherein said MOS portion is a MOS portion providing at least one pair of said base layers and source layers, said gate electrode is disposed over the source layers and .adjacent areas of said well region, and at least one of said base layers is electrically connected to said offset region.

14. A high withstand voltage MIS field effect transistor according to either of claims 9 or 10, wherein a source electrode connected to said source layer is a field plate type source electrode extended toward said drain layer.

15. A high withstand voltage MIS field effect transistor according to either of claims 9 or 10, wherein a drain electrode connected to said drain layer is a field plate type drain electrode extended toward said MOS portion.

16. A high withstand voltage MIS field effect transistor according to either of claims 9 or 10, wherein the drain portion is to provide said drain layer with a high breakdown voltage with an inner portion of said well region being connected to the drain layer.

17. A high withstand voltage MIS field effect transistor according to either of claims 9 or 10, wherein a first conductivity type high concentration buried layer is formed under said drain layer.

18. A high withstand voltage MIS field effect transistor according to either of claims 9 or 10, wherein said source layer is substantially concentrically formed with said drain layer as the center.

19. A high withstand voltage MIS field effect transistor having a second conductivity type well region formed on a first conductivity type semiconductor substrate;

a MOS portion providing, in an outer portion of the well region, a first conductivity type base layer, a second conductivity type source layer formed in the base layer and a gate electrode disposed through an insulating gate film over the source layer and said well region;

a drain portion providing a second conductivity type drain layer formed in an inner portion of said well region, said MOS portion being generally concentrically formed with said drain portion as the center, at least one portion of said well region, said MOS portion and said drain portion being a withstand voltage region capable of enduring a desired withstand voltage with reference to the distance between said MOS portion and said drain portion and having a voltage transferring means capable of transferring the voltage in the withstand voltage region to said well region; and

said voltage transferring means including a plurality of field plates spaced from each other and disposed generally concentrically about said drain portion and within said MOS portion and contacting said withstand voltage region to provide voltage control thereover.

20. A high withstand voltage MIS field effect transistor according to claim 19, wherein said MOS portion and said field plates are disposed about said drain portion with at least some off-concentricity.