Ternary storage dynamic RAM

• US 5,432,735 A
• Filed: 07/08/1993
• Issued: 07/11/1995
• Est. Priority Date: 07/08/1993
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Parks, Terry, Gaskins, Darius D.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/089,165
• Time in Patent Office: 733 Days
• Field of Search: 365/168, 365/222, 365/189.01, 365/230
• US Class Current: 365/168
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 5/16 the pulses having three levels

Abstract

A memory apparatus using conventional DRAMs which uses a ternary representation of stored data. Each DRAM memory cell can thus store three states. The ternary storage memory apparatus includes a binary to ternary converter which receives a first number of binary bits of data during a write operation and generates a second lesser number of data values or voltages using a ternary representation. A second number of memory storage elements are coupled to the binary to ternary converter and store the respective voltage using the above ternary representation. During reads, a ternary to binary converter reads the voltages stored in the memory elements and converts these voltages into the original first number of binary bits that were originally written into the memory storage elements. This allows the use of existing DRAM while considerably increasing the DRAM'"'"'s memory storage density.

Claims

1. A ternary semiconductor storage memory for storing data during write operations and outputting data during read operations, comprising:

a binary to ternary converter which receives a first number of binary data bit values during a write operation and generates a second number of ternary data bit values using a ternary representation, wherein said second number is less than said first number;

a plurality of semiconductor memory storage elements coupled to said binary to ternary converter which stores said second number of ternary data bit values using said ternary representation; and

a ternary to binary converter coupled to said plurality of semiconductor memory storage elements which reads said second number of ternary data bit values using said ternary representation and outputs said first number of binary data bit values during a read operation.

2. The ternary semiconductor storage memory of claim 1, wherein said binary to ternary converter comprises:

a binary to ternary encoder which receives said first number of binary data bit values during said write operation and generates a second number of two-bit values which encode a ternary representation of said binary bits of data; and

a plurality of bit line drivers coupled between said binary to ternary encoder and said plurality of semiconductor memory storage elements, wherein said bit line drivers receive said second number of two-bit values, convert said second number of two-bit values into said second number of ternary data bit values, mad store said ternary data bit values into said semiconductor memory storage elements.

3. The ternary semiconductor storage memory of claim 1, wherein said ternary to binary converter comprises:

a plurality of sense amplifiers coupled to said plurality of semiconductor memory storage elements, wherein said sense amplifiers receive said second number of ternary data bit values using said ternary representation and output a second number of two-bit values; and

a ternary to binary decoder coupled to said plurality of sense amplifiers which receives said second number of two-bit values and converts said second number of two-bit values into said first number of binary data bit values.

4. The ternary semiconductor storage memory of claim 1, wherein each of said second number of ternary data bit values using said ternary representation may comprise one of three values.

5. The ternary semiconductor storage memory of claim 1, wherein each of said second number of ternary data bit values using said ternary representation may comprise either a positive voltage value, a negative voltage value, or a voltage approximately equal to ground.

6. The ternary semiconductor storage memory of claim 1, wherein said semiconductor memory storage elements comprise dynamic random access memory.

7. The ternary semiconductor storage memory of claim 1, wherein said first number is four and said second number is three.

8. A semiconductor memory system with increased storage density, comprising:

a first converter which receives a first number of data values using a first representation of data during a write operation and generates a second number of data bit values using a second representation of data;

a plurality of semiconductor memory storage elements coupled to said first converter which stores said second number of data bit values using said second representation of data; and

a second converter coupled to said plurality of semiconductor memory storage elements which reads said second number of data bit values using said second representation of data and outputs said first number of data values using said first representation of data during a read operation.

9. The semiconductor memory system of claim 8, wherein each of said first number of data values using said first representation of data has one of a first number of states;

and wherein each of said second number of data values using said second representation of data has one of a second number of states.

10. The semiconductor memory system of claim 9, wherein said second number is greater than said first number.

11. The semiconductor memory system of claim 9, wherein said first number is greater than said second number.

12. A ternary semiconductor storage memory for storing data during write operations and outputting data during read operations, comprising:

a binary to ternary encoder which receives a first number of binary data bit values during a write operation and generates a second number of two-bit values which encode a ternary representation of said binary bits of data;

a plurality of bit line drivers coupled to said binary to ternary encoder wherein said bit line drivers receive said second number of two-bit values and convert said second number of two-bit values into a second number of ternary data bit values;

a plurality of semiconductor memory storage elements coupled to said plurality of bit line drivers which store said second number of ternary data bit values using said ternary representation;

a plurality of sense amplifiers coupled to said plurality of semiconductor memory storage elements, wherein said sense amplifiers receive said second number of ternary data bit values and output a second number of two-bit values; and

a ternary to binary decoder coupled to said plurality of sense amplifiers which receives said second number of two-bit values and converts said second number of two-bit values into said first number of binary data bit values.

13. The semiconductor ternary storage memory of claim 13, wherein said first number is four and said second number is three.