Non-volatile sidewall memory cell method of fabricating same

• US 5,432,739 A
• Filed: 06/17/1994
• Issued: 07/11/1995
• Est. Priority Date: 06/17/1994
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Pein, Howard B.
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/261,511
• Time in Patent Office: 389 Days
• Field of Search: 365/185, 365/500, 365/94, 365/104, 257/302, 257/315, 257/318, 257/324, 257/329, 437/52
• US Class Current: 365/185.11
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.

Claims

1. A non-volatile memory formed on a silicon substrate comprising:

a plurality of memory cells arranged in an array of rows of memory cells extending in a bit line direction and columns of memory cells extending in a word line direction, each of said memory cells including a silicon pillar formed in said silicon substrate, a drain region formed on a top side of said pillar, a floating gate surrounding said pillar, separated from said pillar by a first dielectric layer, a second dielectric layer surrounding said floating gate and a control gate surrounding said second dielectric layer;

each of said control gates integrally formed to form a single word line for each column; and

a bit line joined to each of said drain regions of each memory cell in a row extending in said bit line direction, said dimension of said bit line and said pillar in said word line direction being equal to a minimum line width.

2. The memory of claim 1, further including a source region formed in said substrate, said source region shared by each of said memory cells.

3. The memory of claim 1, wherein a distance between contiguous pillars in a column is the minimum line width.

4. The memory of claim 3, wherein a dimension of one of said pillars in said bit line direction is the minimum line width.

5. The memory of claim 4, wherein a distance between contiguous pillars in said bit line direction is greater than the minimum line width.

6. A non-volatile memory cell formed on a silicon substrate comprising:

a silicon pillar formed in said silicon substrate, a drain region formed on a top side of said pillar;

a floating gate surrounding said pillar, separated from said pillar by a first dielectric layer;

a second dielectric layer surrounding said floating gate and a control gate surrounding said second dielectric layer; and

a bit line joined to said drain region extending in said bit line direction, said dimension of said bit line and said pillar in said word line direction being equal to a minimum line width.

7. The memory of claim 6, further including a source region formed in said substrate.

8. The memory of claim 7, wherein a dimension of said pillar in said bit line direction is the minimum line width.