Fail-safe EEPROM based rewritable boot system
First Claim
1. A method of reprogramming computer software instructions in a computer system including a processor with an address base to which the computer software instructions are mapped, said method comprising the steps of:
- (a) providing a writable, non-volatile memory device having a base memory region and an auxiliary memory region;
(b) loading a first set of initialization instructions including a boot routine into said base memory region;
(c) selectively operating said system (i) in a normal mode in which said initialization instructions most recently loaded into said base memory region are mapped to the address base of the processor or (ii) in an auxiliary mode in which initialization instructions copied into said auxiliary memory region are mapped to the address base of the processor, to facilitate initialization of the system;
(d) monitoring said normal mode of operation to determine if an initialization fault is detected and issuing a reset signal to said processor if an initialization fault is detected;
(e) copying said most recently loaded initialization instructions from said base memory region into said auxiliary memory region if no fault is detected and no reset signal is issued, and then loading an updated set of initialization instructions including a boot routine to said base memory region, and repeating steps (c) through (e) until an initialization fault is detected; and
(f) if an initialization fault is detected, switching the operation of said system to the auxiliary mode in response to said reset signal.
0 Assignments
0 Petitions
Accused Products
Abstract
A computer boot strap loading system employs dual, separable EEPROM units to facilitate safe reprogramming of bootstrap loader software. Both EEPROMs are adapted for storing bootstrap loading code. One of these two EEPROM areas is designated as the unit for which the code content will govern operation of the next reboot sequence. Circuitry is provided to monitor progress of a reboot to determine if a defect in the presently utilized reboot sequence is provided. Such a defect triggers a reboot from the other EEPROM as well as to provide a back-up copy of the bootstrap loading code most recently determined to be effective.
-
Citations
18 Claims
-
1. A method of reprogramming computer software instructions in a computer system including a processor with an address base to which the computer software instructions are mapped, said method comprising the steps of:
-
(a) providing a writable, non-volatile memory device having a base memory region and an auxiliary memory region; (b) loading a first set of initialization instructions including a boot routine into said base memory region; (c) selectively operating said system (i) in a normal mode in which said initialization instructions most recently loaded into said base memory region are mapped to the address base of the processor or (ii) in an auxiliary mode in which initialization instructions copied into said auxiliary memory region are mapped to the address base of the processor, to facilitate initialization of the system; (d) monitoring said normal mode of operation to determine if an initialization fault is detected and issuing a reset signal to said processor if an initialization fault is detected; (e) copying said most recently loaded initialization instructions from said base memory region into said auxiliary memory region if no fault is detected and no reset signal is issued, and then loading an updated set of initialization instructions including a boot routine to said base memory region, and repeating steps (c) through (e) until an initialization fault is detected; and (f) if an initialization fault is detected, switching the operation of said system to the auxiliary mode in response to said reset signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 12)
-
-
10. A device for reprogramming computer software instructions in a computer system including a processor with an address base to which the computer software instructions are mapped, said device comprising:
-
(a) a writable, non-volatile memory device electrically connected to said processor, said non-volatile memory device having a base memory region and an auxiliary memory region; (b) circuitry electrically connected to said memory device for loading a first set of initialization instructions including a boot routine into said base memory region; (c) circuitry electrically connecting the processor and said memory device for selectively operating said system (i) in a normal mode in which said initialization instructions most recently loaded into said base memory region are mapped to the address base of the processor, or (ii) in an auxiliary mode in which initialization instructions copied into said auxiliary memory region are mapped to the address base of the processor, to facilitate initialization of the system; (d) circuitry electrically connected to the processor for monitoring said normal mode of operation to determine if an initialization fault is detected and issuing a reset signal to said processor if an initialization fault is detected; (e) circuitry electrically connected to said memory device for copying said most recently loaded initialization instructions from said base memory region into said auxiliary memory region if no fault is detected and no reset signal is issued, and for then loading an updated set of initialization instructions including a boot routine to said base memory region, and for operating said system in said normal mode until an initialization fault is detected; and (f) switching circuitry electrically connected to said memory device for switching the operation of said system to the auxiliary mode if an initialization fault is detected in response to said reset signal. - View Dependent Claims (11, 13, 14, 15, 16, 17, 18)
-
Specification