Integrated circuit lamination process

• US 5,432,999 A
• Filed: 03/21/1994
• Issued: 07/18/1995
• Est. Priority Date: 08/20/1992
• Status: Expired due to Fees

• Current Assignee: David F. Capps, Tyra M. Szwarc
• Original Assignee: David F. Capps, Tyra M. Szwarc
• Inventors: Szwarc, Tyra M., Capps, David F.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/210,921
• Time in Patent Office: 484 Days
• Field of Search: 156/653, 156/655, 156/901, 156/630, 29/830, 29/852
• US Class Current: 438/109
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

A process for forming a multi-layer integrated circuit utilizes a rigid substrate covered by a dissolvable material layer, which is in turn coated by a protective material layer. Electrically conductive posts and a semiconductive material layer are then sequentially formed on the protective material layer. An integrated circuit is formed in the top surface of the semiconductive material layer. Upper conductive pads are formed on exposed ends of the conductive posts. The substrate, dissolvable material layer and protective material layer support each thin integrated circuit layer during fabrication and are removed to enable the integrated circuits to be interconnected into a stack via the conductive posts and pads. In another embodiment, the rigid substrate is formed of a dissolvable material layer which is in turn coated by a protective, insulating layer. The conductive posts and integrated circuit are formed on the substrate prior to dissolving the substrate to expose top and bottom pads attached to opposite ends of the conductive posts. The top and bottom pads of a plurality of like integrated circuits are connected to provide interconnection of multiple dies in a stacked arrangement.

Claims

1. A method for forming a single thin layer integrated circuit device comprising the steps of:

(1) forming a planar substrate of dissolvable material, the substrate having opposed top and bottom surfaces and side edges;

(2) disposing a protective material layer over the dissolvable material layer, with the protective material layer extending over at least the top surface and the side edges of the dissolvable material layer;

(3) disposing a semiconductive material over the protective material layer on the top surface of the substrate;

(4) forming an integrated circuit in the semiconductive material layer; and

(5) separating the substrate from the protective material layer to form a single thin layer integrated circuit device.

2. The method of claim 1 further comprising the step of:

before the step of disposing the protective material layer, forming at least one electrically conductive post on and extending away from the substrate, the electrically conductive post having an exterior surface, a top end, a bottom end and a predetermined length.

3. The method of claim 2 wherein the step of separating comprises the steps of:

removing the protective material layer from at least one of the bottom surface and the side edges of the dissolvable substrate to expose the substrate;

dissolving the dissolvable substrate to separate the substrate from the protective material layer; and

removing the protective layer from the electrically conductive post to expose the top end of at least one electrically conductive post.

4. The method of claim 2 further comprising the steps of:

disposing the protective material layer over the entire surface of the conductive post; and

disposing the semiconductive material layer to at least the top end of the conductive post such that a planar top surface is formed on the semiconductive material exposing the top end of the at least one electrically conductive post.

5. The method of claim 2 further comprising the step of:

forming an electrically conductive pad on the top end of the at least one electrically conductive post.

6. The method of claim 2 further comprising the step of:

forming an electrically conductive base pad on the bottom end of the at least one electrically conductive post in contact with the dissolvable substrate.

7. The method of claim 1 further comprising the step of:

forming the protective material layer of an electrically insulating material.

8. The method of claim 5 further comprising the steps of:

forming an electrically conductive base pad on the bottom end of the at least one electrically conductive post; and

electrically connecting the at least one electrically conductive post and electrically conductive pads on the top and bottom ends of the electrically conductive post of a plurality of like-formed integrated circuits in a stack.

9. A method for fabricating an integrated circuit device comprising the steps of:

(1) forming a dissolvable material layer on a top surface of a planar substrate, the dissolvable material layer terminating in side edges;

(2) disposing a protective material layer over the dissolvable material layer, with the side edges of the protective material layer extending over the side edges of the dissolvable material layer;

(3) forming at least one electrically conductive post on and extending away from the protective material layer, the electrically conductive post having an exterior surface, top and bottom ends, and a predetermined length;

(4) disposing an electrically insulating material layer over the protective material layer and all of the exterior surface of the at least one electrically conductive post;

(5) disposing a semiconductor material over the electrically insulating material layer to at least a top end of the electrically conductive post such that a substantially planar top surface is formed exposing the top end of the at least one electrically conductive post;

(6) forming an integrated circuit in the top surface of the semiconductive material layer;

(7) forming an electrically conductive pad on the top end of the at least one electrically conductive post;

(8) separating the substrate, the dissolvable material layer and the protective material layer from the electrically insulating material layer; and

(9) electrically connecting the electrically conductive posts and pads of a plurality of like formed integrated circuits in a stack.

10. The method of claim 9 further comprising the step of:

forming an electrically conductive base pad on the protective material layer to support the at least one electrically conductive post thereon.

11. The method of claim 9 wherein the step of electrically connecting the posts and pads further comprises:

applying a layer of a low temperature melting point electrically conductive material onto the electrically conductive pad.

12. The method of claim 9 wherein the separating step comprises the steps of:

removing the portion of the protective material layer from the side edges of the dissolvable material layer to expose the side edges of the dissolvable material layer; and

disposing the integrated circuit in a fluid to dissolve and remove the dissolvable material layer from the protective material layer.

13. The method of claim 12 further comprising the step of removing the protective material layer from the insulating material layer.

14. The method of claim 9 further comprising the step of forming a plurality of integrated circuits in the semiconductive material layer, each integrated circuit having a plurality of electrically conductive posts extending therethrough arranged in a predetermined positional arrangement with respect to each integrated circuit.

15. The method of claim 11 further comprising the step of:

stacking a plurality of integrated circuits in alignment with the conductive pads of each integrated circuit connected to the conductive posts of adjacent integrated circuits by the low temperature melting point material layer.