Method of manufacturing semiconductor device with copper core bumps

• US 5,433,822 A
• Filed: 12/22/1992
• Issued: 07/18/1995
• Est. Priority Date: 04/26/1991
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Inventors: Ichikawa, Shingo, Ohi, Masayuki, Tajiri, Takayuki, Shimizu, Junichiro, Kaneko, Hiroyuki, Mimura, Seiichi
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/962,190
• Time in Patent Office: 938 Days
• Field of Search: 257/698, 257/693, 257/780, 257/781, 257/737, 257/738, 257/762, 437/183, 361/398, 361/406, 361/404, 361/402, 361/397, 361/406, 361/409, 156/659.1, 156/661.1, 430/318, 430/325
• US Class Current: 438/614
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/09481 : Via in pad; Pad over filled via if used for surface mounting H05K1/113
• CPC Class Codes: H05K 2201/09563 : Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/1476 : Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 3/427 : initial plating of through-holes in metal-clad substrates

Abstract

A semiconductor device has circuit patterns formed on upper and lower surfaces of a laminated board with both surfaces lined with copper and interconnected by through holes, an IC chip mounted on the upper pattern, and external connection terminals mounted on the lower pattern, the external connection terminals comprising copper core bumps. According to a method of manufacturing such a semiconductor device, the same etching process as pattern etching for forming the circuit pattern are effected in bump forming regions on the circuit pattern formed by the resist pattern.

Claims

1. A method of manufacturing a semiconductor device by forming copper core bumps on a circuit pattern on a circuit board by way of plating using a resist pattern, characterized by forming a solvent-reactive first dry film and a water-soluble second dry film as successive layers as said resist pattern, and removing said second dry film after the copper core bumps are formed.

2. A method of manufacturing a circuit board for a semiconductor device, comprising:

a through hole forming step for forming through holes in a circuit board with thin copper foils on both surfaces of the circuit board,

a plating step for forming copper plates on the surfaces of the circuit board with the through holes,

a patterning step for forming, by using an etching solution, a die pattern region on one surface of the circuit board and bump forming regions on the other surface of the circuit board,

a resist/dry film laminating step for laminating resist/dry films on both surfaces of the circuit board after patterning step to thereby form resist pattern openings at the die pattern region and the bump forming regions, said resist/dry film laminating step including radiation and development,

an activation etching step for removing residues of the resist/dry films dissolved by the radiation and development in the resist/dry film laminating step and deposited on the bump forming regions to thereby activate a surface of copper at the bump forming regions,

a mask/dry film laminating step for laminating a mask/dry film on the resist/dry film at a side of the die pattern region to thereby mask the die pattern region,

a bump forming step for forming copper core bumps on the bump forming regions on the board, and

a mask/dry film developing step for removing the mask/dry film on the resist/dry film.

3. A method of manufacturing a circuit board according to claim 2, wherein removal of residues of the resist/dry films in the activation etching step is made by using the etching solution used in the patterning step.

4. A method of manufacturing a circuit board according to claim 3, wherein the removal of the residues of the resist/dry film in the activation etching step is performed for 5-30 seconds.

5. A method of manufacturing a circuit board according to claim 4, wherein said patterning step includes laminating mask dry films, exposing and developing the mask dry films, and etching the copper plates on the circuit board by the etching solution.