Method of producing a field effect transistor

• US 5,434,094 A
• Filed: 04/08/1994
• Issued: 07/18/1995
• Est. Priority Date: 07/01/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Masahiro, Kobiki, Michihiro, Ishikawa, Takahide
• Primary Examiner(s): Heran, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/224,882
• Time in Patent Office: 466 Days
• Field of Search: 437/40, 437/227, 437/226, 437/902, 437/974, 437/911, 437/912, 148/DIG. 135, 148/DIG. 28
• US Class Current: 438/167
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.

Claims

1. A method of making semiconductor devices comprising:

forming at least one active region at the front surface of a semiconductor wafer having opposed front and rear surfaces;

depositing at least two electrodes in a predetermined relationship with each other on the front surface of the wafer at the active region;

etching at least one via-hole in the wafer from the front surface and extending toward the rear surface adjacent the electrodes at the active region;

etching at least one circumferential separation groove outwardly spaced from the active region in the wafer from the front surface and extending toward the rear surface for separating a portion of said wafer as a semiconductor device;

depositing a first metallic layer in the at least one via-hole and in the at least one separation groove and on the front surface adjacent the via-hole in contact with one of the electrodes and adjacent the separation groove as a measurement electrode;

reducing the thickness of the wafer at the rear surface to expose the first metallic layer;

depositing a second metallic layer on the rear surface in electrical communication with the first metallic layer in the via-hole;

forming a heat sink on the second metallic layer by plating; and

dividing the wafer at the separation groove to form an individual semiconductor device on a heat sink having a metallic protection layer on the lateral walls of the substrate between the front and rear surfaces.

2. The method of claim 1 including forming said active region by implanting impurity ions in the wafer.

3. The method of claim 1 wherein depositing at least two electrodes comprises forming two electrodes making ohmic contact to the active region of the wafer as source and drain electrodes, respectively, and forming a gate electrode making a Schottky barrier with the wafer interposed between said source and drain electrodes.

4. The method of claim 1 including etching the via-hole and the separation groove simultaneously.

5. The method of claim 1 including dry etching the via-hole and the separation groove.

6. The method of claim 1 including wet etching the via-hole and the separation groove.

7. The method of claim 1 including depositing gold as the first metallic layer.

8. The method of claim 1 including reducing the thickness of the wafer by combined mechanical and chemical polishing.

9. The method of claim 1 including forming the heat sink by plating gold on the second metallic layer.

10. The method of claim 1 including dividing said wafer by severing the wafer at the separation groove.

11. The method of claim 1 including dividing said wafer by etching the wafer at the separation groove.