Grounding method to eliminate the antenna effect in VLSI process

• US 5,434,108 A
• Filed: 09/22/1993
• Issued: 07/18/1995
• Est. Priority Date: 09/22/1993
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsue, Chen-Chiu, Ko, Joe
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/124,647
• Time in Patent Office: 664 Days
• Field of Search: 437/228, 437/245, 437/949, 437/195, 437/941, 156/643
• US Class Current: 438/622
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers

Abstract

A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.

Claims

1. A method of subjecting an integrated circuit, having electrically grounded elements and first metal regions on its surface which are connected to device structures, to a plasma process, comprising the steps of:

connecting said first metal regions to said electrically grounded elements;

placing said integrated circuit in a chamber for accomplishing said plasma process;

subjecting said integrated circuit to said plasma process such that said connecting of said first metal regions to said electrically grounded elements prevents damage to said device structures;

removing said integrated circuit from said chamber; and

disconnecting said first metal regions from said electrically grounded elements.

2. The method of claim 1 wherein said processing in a plasma environment is plasma enhanced chemical vapor deposition.

3. The method of claim 1 wherein said processing in a plasma environment is plasma etching.

4. The method of claim 3 wherein said processing in a plasma environment is a sputter etch.

5. The method of claim 1 wherein said first metal regions are contact pads.

6. The method of claim 1 wherein said electrically grounded elements are connected to a grounded substrate through said device structures.

7. A method of subjecting an integrated circuit with CMOS device structures to a plasma process, comprising the steps of:

forming a first layer of metal on said integrated circuit;

patterning said first layer of metal to form contact pads, voltage connection pads, and electrical connections between said contact pads and said voltage connection pads;

connecting said voltage connection pads to ground through said device structures;

processing said integrated circuit in a plasma environment that would normally produce electrical charge build-up at gate oxide of said device structures, but said connection to ground prevents said charge build-up; and

disconnecting said contact pads from said voltage connection pads.

8. The method of claim 7 wherein said processing in a plasma environment is plasma enhanced chemical vapor deposition.

9. The method of claim 7 wherein said processing in a plasma environment is plasma etching.

10. The method of claim 9 wherein said processing in a plasma environment is a sputter etch.

11. The method of claim 7, after the step of said processing in a plasma environment further comprising the steps of:

forming a dielectric layer over said first layer of metal;

forming openings to said electrical connections through said dielectric layer;

forming a second layer of metal over said dielectric layer and contacting said electrical connection through said openings;

removing said second layer of metal except over said contact pad;

removing said first layer of metal under said opening to break said electrical connection; and

forming a passivation layer over the entire integrated circuit, with an opening to an exposed portion of said second metal layer.