ECL-to-BICOMS/CMOS translator

• US 5,434,518 A
• Filed: 05/09/1994
• Issued: 07/18/1995
• Est. Priority Date: 10/02/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Sinh, Nguyen, Yee, Loren
• Primary Examiner(s): Hudspeth, David R.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/239,925
• Time in Patent Office: 435 Days
• Field of Search: 307/475, 307/443, 307/446, 307/570, 326/66, 326/84, 326/110, 326/21, 326/17
• US Class Current: 326/66
• CPC Class Codes: H03K 19/017527 with at least one differential stage

Abstract

An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage having an output node and a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply. A first input stage activates the first output switching means of the output stage in response to one of the differential ECL signals, and a second input stage activates the second output switching means of the output stage in response to the other differential ECL signal. The first input stage includes a first input switching means for coupling a first resistive element between the first voltage supply and the output node of the output stage, and the second input stage includes a second input switching means for coupling a second resistive element between the first voltage supply and the second voltage supply.

Claims

1. An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal, the translator comprising:

an output stage having an output node for outputting the BiCMOS/CMOS level signal, the output stage further having a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply;

a first input stage for activating the first output switching means of the output stage in response to one of the differential ECL signals, the first input stage having a first field effect transistor for coupling a first resistive element between the first voltage supply and the output node of the output stage; and

a second input stage for activating the second output switching means of the output stage in response to the other differential ECL signal, the second input stage having a second field effect transistor for coupling a second resistive element between the first voltage supply and the second voltage supply, the second field effect transistor conducting a steady DC current after the second output switching means is activated.

2. The ECL-to-BiCMOS/CMOS translator of claim 1, wherein the first and second output switching means of the output stage comprise bipolar transistors.

3. The ECL-to-BiCMOS/CMOS translator of claim 2, wherein:

the first field effect transistor of the first input stage comprises a P-channel transistor having its source connected to the first voltage supply, its drain connected to the base of the first output switching means of the output stage and to the first resistive element, and its gate connected to the differential ECL signal; and

the second field effect transistor of the second input stage comprises a P-channel transistor having its source connected to the first voltage supply, its drain connected to the base of the second output switching means of the output stage and to the second resistive element, and its gate connected to the other differential ECL signal.

4. The ECL-to-BiCMOS/CMOS translator of claim 1, further comprising:

an ECL receiver means for receiving a signal ECL signal and for generating the pair of differential ECL signals in response thereto.

5. The ECL-to-BiCMOS/CMOS translator of claim 1, wherein the first input stage further comprises:

a third field effect transistor for coupling the first voltage supply to the output node of the output stage.

6. An ECL-to-BiCMOS/CMOS translator, comprising:

an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a first voltage supply and a second bipolar transistor for coupling the output node to a second voltage supply;

a first input stage, responsive to a first one of a pair of differential ECL signals, for activating the first bipolar transistor of the output stage, the first input stage having a first P-channel transistor for coupling a first resistive element between the first voltage supply and the output node of the output stage; and

a second input stage, responsive to a second one of the pair of differential ECL signals, for activating the second bipolar transistor of the output stage, the second input stage having a second P-channel transistor for coupling a second resistive element between the first voltage supply and the second voltage supply.

7. The ECL-to-BiCMOS/CMOS translator of claim 6, wherein:

the first P-channel transistor of the first input stage has its source connected to the first voltage supply, its drain connected to the base of the first bipolar transistor of the output stage and to the first resistive element, and its gate connected to the first differential ECL signal; and

the second P-channel transistor of the second input stage has its source connected to the first voltage supply, its drain connected to the base of the second bipolar transistor of the output stage and to the second resistive element, and its gate connected to the second differential ECL signal.

8. The ECL-to-BiCMOS/CMOS translator of claim 6, further comprising:

an ECL receiver means for receiving a single ECL signal and for generating the pair of differential ECL signals in response thereto.

9. The ECL-to-BiCMOS/CMOS translator of claim 6, wherein the first input stage further comprises:

a third P-channel transistor for coupling the first voltage supply to the output node of the output stage.

10. An ECL-to-BiCMOS/CMOS translator, comprising:

an ECL receiver means for receiving a single ECL signal and for generating a pair of differential ECL signals in response thereto;

an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a first voltage supply and a second bipolar transistor for coupling the output node to a second voltage supply;

a first input stage for activating the first bipolar transistor of the output stage, the first input stage having a first P-channel transistor having its source connected to the first voltage supply, its drain connected to the base of the first bipolar transistor of the output stage, and its gate connected to a first one of the pair of differential ECL signals, the first input stage further having a resistive element connected between the drain of the first P-channel transistor and the output node of the output stage; and

a second input stage for activating the second bipolar transistor of the output stage, the second input stage having a second P-channel transistor having its source-connected to the first voltage supply, its drain connected to the base of the second bipolar transistor of the output stage, and its gate connected to a second one of the pair of differential ECL signals, the second input stage further having a resistive element connected between the drain of the second P-channel transistor and the second voltage supply.

11. The ECL-to-BiCMOS/CMOS translator of claim 10, wherein the first input stage further comprises:

a third P-channel transistor having its source connected to the first voltage supply, its drain connected to the output node of the output stage, and its gate connected to the first one of the differential ECL signals.

12. An ECL-to-BiCMOS/CMOS translator, comprising;

an ECL receiver stage for generating a pair of differential ECL signals, the ECL receiver stage being connectable to a first voltage supply and to a second voltage supply having a lower voltage potential than the first voltage supply, the differential ECL signals each having a logic high value that has a lower voltage potential than the first voltage supply and a logic low value that has a higher voltage potential than the second voltage supply;

an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a third voltage supply and a second bipolar transistor for coupling the output node to a fourth voltage supply;

a first input stage, responsive to a first one of the pair of differential ECL signals, for activating the first bipolar transistor of the output stage, the first input stage having a first field effect transistor for coupling a first resistive element between the third voltage supply and the output node of the output stage; and

a second input stage, responsive to a second one of the pair of differential ECL signals, for activating the second bipolar transistor of the output stage, the second input stage having a second field effect transistor for coupling a second resistive element between the third voltage supply and the fourth voltage supply.

13. The ECL-to-BiCMOS/CMOS translator of claim 12, wherein the ECL receiver stage comprises:

a third bipolar transistor which generates the first differential ECL signal at its emitter, the third bipolar transistor having its collector connected to the first voltage supply and its emitter connected to a gate of the first field effect transistor; and

a fourth bipolar transistor which generates the second differential ECL signal at its emitter, the fourth bipolar transistor having its collector connected to the first voltage supply and its emitter connected to a gate of the second field effect transistor.

14. The ECL-to-BiCMOS/CMOS translator of claim 13, wherein the ECL receiver stage further comprises:

a third resistive element connected between the emitter of the third bipolar transistor and the second voltage supply; and

a fourth resistive element connected between the emitter of the fourth bipolar transistor and the second voltage supply.

15. The ECL-to-BiCMOS/CMOS translator of claim 14, wherein the ECL receiver stage further comprises:

a fifth bipolar transistor having its collector connected to a base of the third bipolar transistor; and

a sixth bipolar transistor having its collector connected to a base of the fourth bipolar transistor;

wherein, the fifth and sixth bipolar transistors have their emitters connected together.

16. The ECL-to-BiCMOS/CMOS translator of claim 12, wherein the first input stage further comprises:

a third field effect transistor for coupling the third voltage supply to the output node of the output stage.