Circuit for repairing defective read only memories with redundant NAND string

• US 5,434,814 A
• Filed: 10/06/1993
• Issued: 07/18/1995
• Est. Priority Date: 10/06/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Kang-Deog, Do, Jae-Yeong, Cho, Sung-Hee, Lee, Hyong-Gon
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/132,175
• Time in Patent Office: 650 Days
• Field of Search: 365/200, 365/230.03, 365/230.06, 365/185, 365/104
• US Class Current: 365/185.13
• CPC Class Codes: G11C 29/822 for read only memories

Abstract

A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Claims

1. A read only memory comprising:

first and second memory cell arrays each including a plurality of row blocks, each of said row blocks comprising;

a first and second plurality of read only memory cells each arranged in a column direction, said first and second plurality of read only memory cells sharing a bit line in a column direction, a plurality of word lines extending along rows of said first and second plurality of read only memory cells;

first and second row decoders for combining a row address signal, said first and second row decoders selectively driving said plurality of word lines; and

row decoder selecting means for storing therein a plurality of addresses corresponding to ones of said plurality of row blocks including a defective memory cell in respective ones of said first memory cell array, said row decoder selecting means inactivating said first row decoder and activating said second row decoder when said row address signal is equal to an address stored in said row decoder selecting means.

2. A read only memory as claimed in claim 1, wherein said row decoder selecting means comprises:

an output node connected between a power supply voltage and a ground reference voltage, for generating a row decoder selection signal;

at least two n-channel MOS transistors having drain-source channels connected in series between said output node and said ground reference voltage and having gates connected to respective bits of said row address signal; and

at least one of said n-channel MOS transistors being a depletion type MOS transistor.

3. A read only memory comprising:

first and second memory cell arrays each including a plurality of row blocks, each of said row blocks comprising;

a first and second plurality of read only memory cells each arranged in a column direction, said first and second plurality of read only memory cells sharing a bit line in a column direction, a plurality of word lines extending along rows of said first and second plurality of read only memory cells;

a block selection decoder for combining a block selection address signal to generate a block selection signal for selecting one of said plurality of row blocks;

first and second row decoders for combining a row address signal, said first and second row decoders selectively driving said plurality of word lines; and

row decoder selecting means for storing therein a plurality of addresses corresponding to ones of said plurality of row blocks including a defective memory cell in respective ones of said first memory cell array, said row decoder selecting means inactivating said first row decoder and activating said second row decoder when said row address signal is equal to an address stored in said row decoder selecting means.

4. A read only memory as claimed in claim 3, wherein said row decoder selecting means comprises:

an output node connected between a power supply voltage and a ground reference voltage, for generating a row decoder selection signal;

at least two n-channel MOS transistors having drain-source channels connected in series between said output node and said ground reference voltage and having gates connected to said row address signals; and

at least one of said n-channel MOS transistors being a depletion type MOS transistor.