Flash EEPROM system cell array with more than two storage states per memory cell

• US 5,434,825 A
• Filed: 09/03/1993
• Issued: 07/18/1995
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/116,867
• Time in Patent Office: 683 Days
• Field of Search: 365/218, 365/200, 365/201, 365/900, 365/182, 365/185
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of operating an array of electrically erasable and programmable read only memory cells, having means for addressing individual cells to program, read and erase their states, comprising the steps of:

providing individual ones of the memory cells of the array with a field effect transistor including a floating gate and having an effective threshold voltage resulting from a combination of a natural threshold voltage of at least three volts and a voltage responsive to a controllable level of charge on the floating gate, wherein said natural threshold voltage corresponds to the threshold voltage when the floating gate has a level of charge equal to zero,

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the individual cells in excess of two,

erasing a group of said memory cells by driving the effective threshold voltage of the individual cells in said group to a base level by altering the charge on the floating gates of the cells in said group, and

thereafter programming at least one cell in said group of cells to one of said plurality of detectable states by altering the charge on the floating gate of said at least one cell until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels.

2. The method of claim 1 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

3. The method of claim 1 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing exactly four such threshold voltage levels, whereby said at least one cell can store two bits of information.

4. The method of claim 1 wherein the threshold voltage level establishing step includes selecting at least two of said plurality of effective threshold voltage levels to be less than said natural threshold voltage level.

5. The method of claim 1 wherein the threshold voltage level establishing step includes selecting all of said plurality of effective threshold voltage levels to be less than said natural threshold voltage level.

6. The method of claim 1 wherein the programming step includes alternately pulsing said at least one cell and reading a current therethrough until the current level reaches that corresponding to a desired one of said plurality of threshold voltage levels.

7. The method of claim 1 wherein the programming step includes alternately pulsing said at least one cell with short programming pulses and reading a current therethrough after each such programming pulse until the current level reaches that corresponding to the desired one of said plurality of effective threshold levels, each one of said short programming pulses being insufficient to change said effective threshold voltage by more than approximately one-half the difference of between any two adjacent of said plurality of effective threshold voltage levels.

8. The method of claim 1 wherein the erasing step includes alternately pulsing the group of said memory cells and reading a current therethrough until the current level reaches that corresponding to said base threshold level, the magnitude of each such pulse increasing from pulse to pulse.

9. The method of claim 8 which comprises the additional step of accumulating a count equal to a total number of times that said group of cells has been erased to said base threshold level.

10. The method of claim 1 wherein the erasing step includes alternately pulsing the group of cells with an erase pulse and reading a current therethrough until the current level reaches that corresponding to said base threshold level, the magnitude and duration of each such erase pulse being chosen so that the first erase pulse is insufficient to fully erase said group of cells and each subsequent erase pulse has its magnitude increased by a fixed increment until the group of cells is fully erased.

11. The method of claim 10 which comprises the additional step of, after the group of cells has been erased to the base threshold level, incrementing a counter by one, thereby allowing the total number of times the group of cells has been erased to be monitored.

12. The method of claim 10 wherein the step of erasing the group of cells additionally includes discontinuing the erase pulses after a predetermined number of erase pulses has been applied.

13. The method of claim 10 wherein said fixed increment is within a range of approximately one-half to one volt.

18. The method of claim 1 which comprises the additional step of, after the cell has been erased to its base threshold level, incrementing a counter by one, thereby allowing the total number of times the cell has been erased to be monitored.

35. The method of claim 1 wherein the erasing step includes driving the effective threshold voltage of said cells in said group to a level that is lower than the lowest of the plurality of detectable states by removing negative charge from the floating gates of said group of cells, and wherein the programming step includes adding negative charge to the floating gate of said at least one cell.

14. In an array of a plurality of electrically erasable and programmable read only memory cells wherein each cell includes a split-channel field effect transistor that has in a semiconductor substrate a source and drain separated by a channel region, a floating gate positioned over only a first portion of and insulated from the channel region adjacent the drain, and a control gate extending over and insulated from the floating gate and a second portion of the channel adjacent the source, the first portion of said transistor having an effective threshold voltage resulting from a combination of a natural threshold voltage and a voltage responsive to a controllable level of charge on the floating gate, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, and the second portion of said transistor being connected in series with said first portion and having a conductance determined by a voltage on said control gate, a system for erasing, programming and reading the memory state of the cells in said array, comprising:

means operably connected to said array for addressing a selected one or group of the plurality of memory cells,

erasing means operably connected to said array for driving the effective threshold voltage of an addressed cell or group of cells to a base level by altering the charge on each addressed cell'"'"'s floating gate,

programming means operably connected to said array for altering the charge on the floating gate of an addressed cell until its said effective threshold voltage is substantially equal to one of a plurality of effective threshold voltage levels in excess of two corresponding to a plurality of individual detectable states in excess of two, whereby each cell of the array is programmable into one of said detectable states,

reading means operably connected to said array for determining the amount of current that flows in an addressed cell, whereby the state of an addressed cell is determined from its measured current level, and

wherein said natural threshold voltage is established at a level of at least three volts.

15. The memory array erasing, programming and reading system according to claim 14 wherein said programming means includes means for adding negative charge to the floating gate of an addressed cell until its effective threshold voltage is substantially equal to one of at least four effective threshold voltage levels, whereby each cell of the array is programmable into four or more states.

16. The memory array erasing, programming and reading system according to claim 14 wherein said programming means includes means for applying a first high positive voltage to the control gate of an addressed cell transistor and a second high positive voltage to the drain of said addressed cell transistor while maintaining its source and substrate at essentially zero volts.

17. The memory array erasing, programming and reading system according to claim 16 wherein said array of memory cells includes a common connection between the control gates of memory cells in a row, and wherein said programming means additionally includes means for applying said first high positive voltage to said common connection of a row of cells and for applying said second high positive voltage to only the drains of those memory cells in said row which have not yet reached their desired particular programmed effective threshold voltage levels.

19. For an array of electrically alterable memory cells having means for addressing individual cells to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of altering a memory state of an addressed cell of the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two, wherein a majority of said plurality of effective threshold levels result from a net positive charge on the floating gate,

presetting the effective threshold voltage of the addressed cell to a predetermined level by altering the amount of charge on the floating gate, and

setting the addressed cell to one of its said plurality of states by altering the amount of charge on the floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels.

20. The method of claim 19 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

21. The method of claim 19 wherein the threshold voltage level establishing step includes selecting all of said plurality of effective threshold voltage levels to result from a net positive charge on the floating gate.

22. The method of claim 19 wherein the given threshold level of the memory cell transistors is at least three volts.

23. The method of any one of claims 19-22 wherein the step of setting the cell to any one of its said plurality of threshold voltage levels includes alternately pulsing the cell with voltage pulses and reading a current therethrough after each such pulse until the current level reaches that corresponding to the desired one of said plurality of effective threshold levels, each one of said pulses being insufficient to change said effective threshold voltage by more than approximately one-half the difference of between any two adjacent of said plurality of threshold voltage levels.

24. The method of any one of claims 19-22 wherein the step of presetting the cell includes alternately pulsing the cell with an erase pulse and reading a current therethrough until the current level reaches that corresponding to said predetermined level, the magnitude and duration of each such erase pulse being chosen so that the first erase pulse is insufficient to fully erase said cell and each subsequent erase pulse has its magnitude increased by a fixed increment until the cell is fully erased.

25. The method of any one of claims 19-22 wherein the step of presetting the addressed cell includes alternately pulsing the addressed cell with an erase pulse and reading its effective threshold level until either said effective threshold level reaches said predetermined level or the number of erase pulses applied has exceeded a preset number.

26. The method according to any one of claims 19-22 which comprises the additional step of accumulating a count equal to a total number of times that cell has been preset.

36. The method of any one of claims 19-22 wherein the presetting step includes establishing the predetermined effective threshold voltage of the addressed cell at a level lower than the lowest of said plurality of effective threshold voltage levels corresponding to the plurality of states of the cell by removing negative charge from the floating gate, and the setting step includes adding negative charge to the floating gate of the addressed cell.

27. A memory system formed of an array of split-channel EEPROM cells, wherein individual cells comprise:

source and drain regions formed in said substrate surface and separated by a channel region divided into first and second adjacent portions,

a control gate positioned adjacent said source region and extending across the first portion of said channel region with a first gate dielectric layer therebetween in a manner to control conduction through the first channel portion in accordance with a level of voltage applied to the control gate, thereby forming a first transistor characterized by a fixed threshold in response to a voltage applied to the control gate,

a floating gate positioned adjacent said drain region and extending across the second portion of said channel region with a second gate dielectric layer therebetween in a manner to control conduction through the second channel portion in accordance with a level of electronic charge stored thereon, said control gate also extending over at least a portion of the floating gate and being insulated therefrom, thereby forming a second transistor having a threshold level in response to a voltage applied to the control gate that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, and

an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween,

and wherein the system additionally comprises means operably connectable with at least said source, said drain, said control gate and said erase gate of an addressed one or more of the cells within the array for programming and reading any one of more than two programmable threshold states of the second transistor of said addressed one or more cells that results from any respective one of more than two levels of net charge being placed onto the floating gate, said second transistor given threshold level being established sufficiently high so that a majority of said more than two programmable threshold states result from a net positive charge on the floating gate.

28. The memory system according to claim 27 wherein said given threshold level of the second transistor of the individual cells is higher than the threshold level of the first transistor of the individual cells.

29. The memory system according to claim 27 wherein said given threshold level of the second transistor of the individual cells is at least three volts.

30. The memory system according to claim 29 wherein the fixed threshold level of the first transistor of the individual cells is approximately one volt.

31. The memory system according to claim 27 wherein said second transistor given threshold level is established sufficiently high in order that all of said programmable threshold states result from a net positive charge on the floating gate.

32. The memory system according to claim 27 wherein said more than two programmable threshold states of the second transistor of the individual cells is exactly three.

33. The memory system according to claim 27 wherein said more than two programmable threshold states of the second transistor of the individual cells is exactly four.

34. The memory system according to claim 27 wherein said programming and reading means comprises:

means electrically connectable with at least said source, drain and erase gate of said addressed one or more cells for causing electronic charge to be removed from their floating gates and onto their erase gates until their floating gates become positively charged to at least a given amount,

means electrically connectable with at least said source, drain and control gate of said addressed one or more cells for causing electronic charge to be added to their floating gates to raise the amount of electronic charge stored thereon from said at least a given positive charge to one of said more than two programmable threshold states, and

means electrically connectable with at least said source, drain and control gate of said addressed one or more cells for reading the levels of charge stored on their floating gates and determining in which of said more than two programmable threshold states said levels lie, thereby to read one of said more than two programmable threshold states.

37. For an array of electrically alterable memory cells having means for addressing individual cells to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of altering the state of an addressed cell of the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two, wherein a majority of said plurality of effective threshold levels result from a net positive charge on the floating gate, and

setting the effective threshold voltage level of the addressed cell to one of said plurality of levels by altering the amount of charge on the floating gate of the addressed cell until the effective threshold voltage of the addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, whereby the state of the addressed cell is set to one of said plurality of states.

38. The method of claim 37 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

39. The method of claim 37 wherein the threshold voltage level establishing step includes selecting all of said plurality of effective threshold voltage levels to result from a net positive charge on the floating gate.

40. The method of any one of claims 37-39 wherein the given threshold level of the memory cell transistors is at least three volts.

41. For an array of electrically alterable memory cells having means for addressing individual cells to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of altering a memory state of an addressed cell of the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two,

presetting the effective threshold voltage of the addressed cell to a predetermined level by altering the amount of charge on the floating gate,

setting the addressed cell to one of its said plurality of states by altering the amount of charge on the floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels, and

wherein said given threshold voltage level is established to be at least three volts.

42. The method of claim 41 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

43. The method of claim 41 wherein the step of setting the cell to any one of its said plurality of threshold voltage levels includes alternately pulsing the cell with voltage pulses and reading a current therethrough after each such pulse until the current level reaches that corresponding to the desired one of said plurality of effective threshold levels, each one of said pulses being insufficient to change said effective threshold voltage by more than approximately one-half the difference of between any two adjacent of said plurality of threshold voltage levels.

44. The method of claim 41 wherein the step of presetting the cell includes alternately pulsing the cell with an erase pulse and reading a current therethrough until the current level reaches that corresponding to said predetermined level, the magnitude and duration of each such erase pulse being chosen so that the first erase pulse is insufficient to fully erase said cell and each subsequent erase pulse has its magnitude increased by a fixed increment until the cell is fully erased.

45. The method of claim 41 wherein the step of presetting the addressed cell includes alternately pulsing the addressed cell with an erase pulse and reading its effective threshold level until either said effective threshold level reaches said predetermined level or the number of erase pulses applied has exceeded a preset number.

46. The method of claim 41 which comprises the additional step of accumulating a count equal to a total number of times that cell has been preset.

47. For an array of electrically alterable memory cells having means for addressing individual cells to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of altering the state of an addressed cell of the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two,

setting the effective threshold voltage level of the addressed cell to one of said plurality of levels by altering the amount of charge on the floating gate of the addressed cell until the effective threshold voltage of the addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, whereby the state of the addressed cell is set to one of said plurality of states, and

wherein said given threshold voltage level is established to be at least three volts.

48. The method of claim 47 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

49. For an array of electrically alterable memory cells divided into blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, said memory cells individually including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two,

setting the effective threshold voltage level of at least one addressed cell within one of said blocks to one of said plurality of levels by altering the amount of charge on the floating gate of said at least one addressed cell until the effective threshold voltage of said at least one addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, whereby the state of said at least one addressed cell is set to one of said plurality of states, and

accumulating a count equal to a total number of times that cells within individual ones of said blocks of cells have been set to one of said plurality of states.

50. The method according to claim 49 wherein the step of accumulating a count for individual ones of said blocks includes storing the count within said individual ones of said blocks.

51. The method according to claim 49, additionally comprising the steps of providing at least one redundant block of memory cells, and, in response to the count for an individual one of said blocks exceeding a set number, substituting said redundant block for said individual one of said blocks.

52. The method according to claim 49, additionally comprising the steps of providing a plurality of redundant memory cells, and, in response to said at least one addressed memory cell being bad, substituting at least one of said redundant cells for said at least one addressed cell.

53. The method according to any one of claims 49-52 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

54. For a system containing an array of electrically alterable memory cells partitioned into a plurality of distinct blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating said memory system, comprising the steps of:

establishing (a) a plurality of effective memory cell threshold voltage levels in excess of two that correspond to a plurality of individually detectable memory cell states in excess of two, and (b) an effective base memory cell threshold voltage level,

providing redundant cells for substitution in place of any bad cells within said blocks of memory cells,

simultaneously altering the amount of charge on the floating gates of the memory cells within at least one of said blocks of cells toward said effective base threshold voltage level, thereby to preset the effective threshold voltage thereof,

altering the amount of charge on the floating gate of at least one of the memory cells within said at least one of said blocks of cells in order to move its effective threshold voltage toward a desired one of said plurality of effective threshold voltage levels, thereby to set said at least one of the memory cells to one of said plurality of detectable states,

generating addresses of any cells within said at least one of said blocks of cells that are not altered to a desired effective threshold voltage level, and

wherein the setting step includes substituting at least one of said redundant cells for any of said at least one of the memory cells whose addresses have been so generated.

55. The method according to claim 54, additionally comprising the step of separately accumulating a count of a total number of times that the individual blocks of cells have been preset.

56. The method according to claim 54 wherein the presetting step includes continuing to alter the amount of charge on the floating gates of the memory cells within said at least one of said blocks of cells until the effective threshold level of all but N number of memory cells within said at least one block reaches said effective base threshold level, and wherein the step of generating addresses includes generating addresses of said N number of cells.

57. The method according to any one of claims 54-56 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

58. For an array of electrically alterable memory cells divided into blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, said memory cells individually including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two,

setting the effective threshold voltage level of each of a plurality of cells addressed within one of said blocks to one of said plurality of levels by altering the amount of charge on the floating gate of said each of the plurality of cells until the cell'"'"'s effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels, whereby the states of said plurality of addressed cells are individually set to one of said plurality of states,

designating as a redundant block at least one of said blocks of cells other than said one of said blocks, and

substituting said redundant block of cells for said one of said blocks, whereby a plurality of cells within said redundant block of cells become addressable for setting their effective threshold voltage levels to one of said plurality of levels.

59. The method of claim 58, additionally comprising the steps of monitoring the individual blocks of cells, and, in response to determining that an endurance limit of said one of said blocks of cells has been reached, initiating the redundant block substituting step.