Communications controller utilizing an external buffer memory with plural channels between a host and network interface operating independently for transferring packets between protocol layers

• US 5,434,976 A
• Filed: 10/22/1992
• Issued: 07/18/1995
• Est. Priority Date: 09/28/1992
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Ta, John, Chan, deceased, Philip, Tan, Min P., Fuh, Eric
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Kim, Sang Hui
• Application Number:
  US07/965,145
• Time in Patent Office: 999 Days
• Field of Search: 395/200, 395/275, 395/250
• US Class Current: 709/234
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 using an external memory or storage device
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.

Claims

1. A data communication controller formed on a single integrated circuit chip, for use in a local area network having a communication medium and a network communication protocol and being interfaceable with an external system bus including an external system data bus and an external system address bus, said external system data bus and said external system address bus being operably associated with a host processor and external buffer memory including a plurality of memory storage elements for buffering data packets including transmit packets and receive packets, and each said transmit packet and said receive packet being composed of one or more data words, said data communication controller comprising:

data communication means, operably interfaceable with said communication medium, for transmitting transmit packets over said communication medium and receiving receive packets from over said communication medium, said data communication means further including

a transmit data word queue for buffering the data words associated with one or more said transmit packets to be transmitted over said communication medium, and

a receive data word queue for buffering the data words of one or more said receive packets received from over said communication medium;

system bus interface means for interfacing said data communication controller with said external system bus, and further including

an input data word queue for buffering the data words transferred from said host processor over said external system bus to said data communication controller, and

an output data word queue for buffering data words to be transferred from said data communication controller over said external system bus to said external buffer memory;

first data transfer means for transferring data words along a second data channel defined from said input data word queue to said transmit data word queue;

second data transfer means for transferring data words along a second data channel defined from said receive data word queue to said output data word queue;

internal data storage memory for storing external address data specifying the location of predefined memory structures maintained in said external buffer memory;

third data transfer means for transferring data words along a third data channel defined from said input data word queue to said internal data storage memory;

fourth data transfer means for transferring data words along a fourth data channel defined from said internal data storage memory to said output data word queue;

memory access control means for directly controlling access to memory storage elements in said external buffer memory, and further including

first means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said transmit data word queue,

second means for controlling the transfer of data words from said receive data word queue to said output data word queue and thence to said external data buffer memory,

third means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said internal data storage memory,

fourth means for controlling the transfer of data words from said internal data storage means to said output data word queue and thence to said external buffer memory,

a first external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory from which data words are to be read and transferred to said input data word queue,

a second external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said output data word queue,

a third external address counter for incrementally generating from a preselected external address a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory which data words are to be read and transferred to said input data word queue,

a fourth external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory into which data words are to be written from said output data word queue, and

an external address queue for buffering a plurality of said external addresses;

a first processing means operably associated with said data communication means, and having

means for independently accessing said internal data storage memory, and

means for selectively processing said receive packets so as to perform said network communication protocol at said data communication controller; and

a second processing means independent of said first processing means, operably connected to said memory access control means, and having

means for independently accessing said internal data storage memory,

means for managing the transfer of receive packets from said data communication means to said system bus interface means, and from said system bus interface means to said external buffer memory for storage therein, and

means for managing the transfer of transmit packets from said external buffer memory to said system bus interface means and from said system bus interface means to said data communication means, for transfer to said communication medium.

2. The data communication controller of claim 1, wherein said external address queue comprises:

a plurality of address storage locations for buffering said plurality of said external addresses;

an address insertion location operably associated with said first, second, third and fourth external address counters, for insertion of each said external address into said external address queue;

an address removal location operably associated with said external address system bus, for removal of each said external address from said external address queue and placement on said external system address bus; and

a first tag bit sequence queue having a first plurality of tag bit sequence storage locations for storage of a first plurality tag bit sequences, each said first tag bit sequence storage location being associated with one said address storage location, and said first tag bit sequence queue further having a first tag bit sequence insertion location for insertion of each tag bit sequence into said first tag bit sequence queue and a first tag bit sequence removal location for removal of each said tag bit sequence from said first tag bit sequence queue.

3. The data communication controller of claim 2, wherein said memory access control means further comprises:

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said first tag bit sequence insert location of said first tag bit sequence queue,

wherein each said tag bit sequence is associated with one said external address and indicative of one of said first, second, third and fourth data channels within said data communication controller, over which a corresponding data word is to be transferred under the direct control of said memory access control means.

4. The data communication controller of claim 3, wherein said input data word queue comprises

a plurality of input data word storage locations for buffering a plurality of data words providable from said external buffer memory,

an input data word insertion location operably associated with said external system data bus, for insertion of each said data word into said input data word queue, and

an input delta word removal location operably associated with said first data transfer means and third data transfer means, for removal of each said input data word from said input data word queue;

and

wherein said output data word queue comprises

a plurality of output data word storage locations for buffering a plurality of data words provided from one of said receive data word queue and said internal data storage memory,

an output data word insertion location operably associated with said second data transfer means and said fourth data transfer means, for insertion of each said data word into said output data word queue, and

an output data word removal location operably associated with said external system data bus for removal of each said data word from said output data word queue.

5. The data communication controller of claim 4, wherein said input data word queue further comprises:

a second tag bit sequence queue having a second plurality of tag bit sequence storage locations for storage of a second plurality of tag bit sequences, each said tag bit storage location being associated with one said input data word storage location, and said second tag bit sequence queue further having a second tag bit sequence insertion location for insertion of each said tag bit sequence into said second tag bit sequence queue, and a second tag bit sequence removal location for removal of each said tag bit sequence from said second stage bit sequence queue; and

means for transferring each said tag bit sequence from said first tag bit sequence queue to said second tag bit sequence insertion location.

6. The data communication controller of claim 5, wherein said memory access control means further comprises:

pointer generating means for generating and sequentially incrementing address pointers which define

(i) the address insertion and removal locations of said external address queue,

(ii) the first tag bit sequence insertion and removal locations of said first tag bit sequence queue,

(iii) the input data word insertion and removal locations of said input data word queue,

(iv) the second tag bit sequence insertion and removal locations of said second tag bit sequence queue, and

(v) the output data word insertion and removal locations of said output data word queue.

7. The data communication controller of claim 1, wherein said memory access control means further comprises:

a first internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory into which data words are to be sequentially read from said output data word queue; and

a second internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory from which data words are to read and sequentially written into said input data word insertion location of said input data word queue.

8. The data communication controller of claim 6, wherein said preselected external addresses are provided to said first, second, third and fourth external address counters by said second processing means.

16. The apparatus of claim 6, wherein said preselected external addresses are provided to said first, second, third and fourth external address counters by said second processing means.

9. Apparatus for use in a local area network having a communication medium and a network communication protocol, said apparatus comprising:

(A) an external buffer memory having a plurality of memory storage elements, for buffering data packets including transmit packets and receive packets, said external buffer memory being interfaceable with an external system bus including an external system data bus and an external system address bus, each being operably associated with a host processor; and

(B) a data communication controller interfaceable with said external system bus, said data communication controller including;

data communication means, being operably interfaceable with said communication medium, for transmitting transmit packets over said communication medium and receiving receive packets from over said communication medium, and each said transmit packet and each said receive packet being composed of one or more data words;

system bus interface means for interfacing said data communication controller with said external system bus, said system bus interface means further including

an input data word queue for buffering the data words transferred from said host processor over said external system bus to said data communication controller, and

an output data word queue for buffering data words transferred from said data communication controller over said external system bus to said external buffer memory;

a transmit data word queue for buffering the data words associated with one or more said transmit packets to be transmitted over said communication medium;

a receive data word queue for buffering the data words of one or more said receive packets received from over said communication medium;

first data transfer means for transferring data words along a first data pathway defined from said input data word queue to said transmit data word queue;

second data transfer means for transferring data words along a second data pathway defined from said receive data word queue to said output data word queue;

a third data transfer means for transferring data words along a third data pathway defined from said input data word queue to said internal data storage memory, and

a fourth data transfer means for transferring data words along a fourth data pathway defined from said data storage memory to said output data word queue;

memory access control means for directly controlling access to said memory storage elements in said external buffer memory, said memory access control means being operably connected to said second processing means and including

first means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said transmit data word queue,

second means for controlling the transfer of data words from said receive data word queue to said output data word queue and thence to said external data buffer memory,

third means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said internal data storage memory,

fourth means for controlling the transfer of data words from said internal data storage means to said output data word queue and thence to said external buffer memory,

a first external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory from which data words are to be read and transferred to said input data word queue,

a second external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory into which data words are to be written from said output data word queue,

a third external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory which data words are to be read and transferred to said input data word queue,

a fourth external address counter for incrementally generating from a preselected external address, a sequence of external addresses specifying the location of a sequence of data storage elements in said external buffer memory into which data words are to be written from said output data word queue, and

an external address queue for buffering a plurality of said external addresses;

a first processing means operably associated with said data communication means, for selectively processing said receive packets so as to perform said network communication protocol at said data communication controller; and

a second processing means independent of said first processing means, and having

means for managing the transfer of receive packets from said data communication means to said system bus interface means, and from said system bus interface means to said external buffer memory for storage therein, and

means for managing the transfer of transmit packets from said external buffer memory to said system bus interface means and from said system bus interface means to said data communication means, for transfer to said communication medium.

10. The apparatus of claim 9, wherein said external address queue comprises:

a plurality of address storage locations for buffering said plurality of said external addresses;

an address insertion location operably associated with said first, second, third and fourth external address counters, for insertion of each said external address into said external address queue;

an address removal location operably associated with said external address system bus, for removal of each said external address from said external address queue and placement on said external system address bus; and

a first tag bit sequence queue having a first plurality of tag bit sequence storage locations for storage of a first plurality tag bit sequences, each said first tag bit sequence storage location being associated with one said address storage location, and said first tag bit sequence queue further having a first tag bit sequence insertion location for insertion of each tag bit sequence into said first tag bit sequence queue and a first tag bit sequence removal location for removal of each said tag bit sequence from said first tag bit sequence queue.

11. The apparatus of claim 9, wherein said memory access control means further comprises:

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said first tag bit sequence insert location of said first tag bit sequence queue, wherein each said tag bit sequence is associated with one said external address and indicative of one of said first, second, third and fourth data channels within said data communication controller over which a corresponding data word is to be transferred under the direct control of said memory access control means.

12. The apparatus of claim 11, wherein said input data word queue comprises:

a plurality of input data word storage locations for buffering a plurality of data words providable from said external buffer memory,

an input data word insertion location operably associated with said external system data bus, for insertion of each said data word into said input data word queue, and

an input data word removal location operably associated with said first data transfer means and third data transfer means, for removal of each said input data word from said input data word queue; and

wherein said output data word queue comprises;

an plurality of output data word storage locations for buffering a plurality of data words provided from one of said receive data word queue and said internal data storage memory;

an output data word insertion location operably associated with said second data transfer means and said fourth data transfer means, for insertion of each said data word into said output data word queue, and an output data word removal location operably associated with said external system data bus for removal of each said data word from said output data word queue.

13. The apparatus of claim 11, wherein said input data word queue further comprises:

a second tag bit sequence queue having a second plurality of tag bit sequence storage locations for storage of a second plurality of tag bit sequences, each said tag bit storage location being associated with one said input data word storage location, and said second tag bit sequence queue further having a second tag bit sequence insertion location for insertion of each said tag bit sequence into said second tag bit sequence queue, and a second tag bit sequence removal location for removal of each said tag bit sequence from said second stage bit sequence queue; and

means for transferring each said tag bit sequence from said first tag bit sequence queue to said second tag bit sequence insertion location.

14. The apparatus of claim 13, wherein said memory access control means further comprises:

pointer generating means for generating and sequentially incrementing address pointers which define

(i) the address insertion and removal locations of said external address queue,

(ii) the first tag bit sequence insertion and removal locations of said first tag bit sequence queue,

(iii) the input data word insertion and removal locations of said input data word queue,

(iv) the second tag bit sequence insertion and removal locations of said second tag bit sequence queue, and

(v) the output data word insertion and removal locations of said output data word queue.

15. The apparatus of claim 9, wherein said memory access control means further comprises:

a first internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory into which data words are to be sequentially read from said output data word queue; and

a second internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory from which data words are to read and sequentially written into said input data word insertion location of said input data word queue.

17. A data communication controller formed on a single integrated circuit chip, for use in a local area network having a communication medium and a network communication protocol and being interfaceable with an external system bus including an external system data bus and an external system address bus, said external system data bus and said external system address bus being operably associated with a host processor and external buffer memory including a plurality of memory storage elements for buffering data packets including transmit packets and receive packets, each said transmit packet and said receive packet being composed of one or more data words, said data communication controller comprising:

data communication means, operably interfaceable with said communication medium, for transmitting transmit packets over said communication medium, said data communication means further including

a transmit data word queue for buffering the data words associated with one or more said transmit packets to be transmitted over said communication medium, and

a receive data word queue for buffering the data words of one or more said receive packets received from over said communication medium;

system bus interface means for interfacing said data communication controller with said external system bus, said system bus interface means further including

and input data word queue for buffering the data words transferred from said host processor over said external system bus to said data communication controller, and

an output data word queue for buffering data words to be transferred from said data communication controller over said external system bus to said external buffer memory;

first data transfer means for transferring data words along a second data channel defined from said input data word queue to said transmit data word queue;

second data transfer means for transferring data words along a second data channel defined from said receive data word queue to said output data word queue;

a third data transfer means for transferring data words along a third data channel defined from said input data word queue to said internal data storage memory;

a fourth data transfer means for transferring data words along a fourth data channel defined from said internal data storage memory to said output data word queue;

internal data storage memory for storing external address data specifying the location of predefined memory structures maintained in said external buffer memory;

memory access control means for directly controlling access to memory storage elements in said external buffer memory, said memory access control means further including

first means for controlling the transfer of data words form said external data buffer memory to said input data word queue and thence to said transmit data word queue,

second means for controlling the transfer of data words from said receive data word queue to said output data word queue and thence to said external data buffer memory,

third means for controlling the transfer of data words for said receive data word queue to said output data word queue and thence to said external data buffer memory,

third means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said internal data storage memory, and

fourth means for controlling the transfer of data words from said internal data storage means to said output data word queue and thence to said external buffer memory

an external address queue for buffering a plurality of said external addresses;

a first processing means operably associated with said data communication means, and having

means for independently accessing said internal data storage memory, and

means for selectively processing said receive packets so as to perform said network communication protocol at said data communication controller; and

a second processing means independent of said first processing means and operably connected to said memory access control means, and having

means for independently accessing said internal data storage memory,

means for managing the transfer of receive packets from said data communication means to said system bus interface means, and from said system bus interface means to said external buffer memory for storage therein, and means for managing the transfer of transmit packets from said external buffer memory to said system bus interface means and from said system bus interface means to said data communication means for transfer to said communication medium.

18. The data communication controller of claim 17, wherein said external address queue comprises:

a plurality of address storage locations for buffering said plurality of said external addresses;

an address insertion location operably associated with said first, second, third and fourth external address counters, for insertion of each said external address into said external address queue;

an address removal location operably associated with said external address system bus, for removal of each said external address from said external address queue and placement on said external system address bus; and

a first tag bit sequence queue having a first plurality of tag bit sequence storage locations for storage of a first plurality tag bit sequences, each said first tag bit sequence storage location being associated with one said address storage location, and said first tag bit sequence queue further having a first tag bit sequence insertion location for insertion of each tag bit sequence into said first tag bit sequence queue and a first tag bit sequence removal location for removal of each said tag bit sequence from said first tag bit sequence queue.

19. The data communication controller of claim 18, wherein said memory access control means further comprises:

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said first tag bit sequence insert location of said first tag bit sequence queue, wherein each said tag bit sequence is associated with one said external address and indicative of one of said first, second, third and fourth data channels within said data communication controller over which a corresponding data word is to be transferred under the direct control of said memory access control means.

20. The data communication controller of claim 18, wherein said input data word queue comprises:

a plurality of input data word storage locations for buffering a plurality of data words providable from said external buffer memory;

an input data word insertion location operably associated with said external system data bus, for insertion of each said data word into said input data word queue; and

an input data word removal location operably associated with said first data transfer means and third data transfer means, for removal of each said input data word from said input data word queue, and wherein said output data word queue comprises;

an plurality of output data word storage locations for buffering a plurality of data words provided from one of said receive data word queue and said internal data storage memory;

an output data word insertion location operably associated with said second data transfer means and said fourth data transfer means, for insertion of each said data word into said output data word queue, and

an output data word removal location operably associated with said external system data bus for removal of each said data word from said output data word queue.

21. The data communication controller of claim 20, wherein said input data word queue further comprises:

a second tag bit sequence queue having a second plurality of tag bit sequence storage locations for storage of a second plurality of tag bit sequences, each said tag bit storage location being associated with one said input data word storage location, and said second tag bit sequence queue further having

a second tag bit sequence insertion location for insertion of each said tag bit sequence into said second tag bit sequence queue,

a second tag bit sequence removal location for removal of each said tag bit sequence from said second stage bit sequence queue, and

means for transferring each said tag bit sequence from said first tag bit sequence queue to said second tag bit sequence insertion location.

22. The data communication controller of claim 21, wherein said memory access control means further comprises:

pointer generating means for generating and sequentially incrementing address pointers which define

(i) the address insertion and removal locations of said external address queue,

(ii) the first tag bit sequence insertion and removal locations of said first tag bit sequence queue,

(iii) the input data word insertion and removal locations of said input data word queue,

(iv) the second tag bit sequence insertion and removal locations of said second tag bit sequence queue, and

(v) the output data word insertion and removal locations of said output data word queue.

23. The data communication controller of claim 17, wherein said memory access control means further comprises:

a first internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory into which data words are to be sequentially read from said output data word queue; and

a second internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory from which data words are to read and sequentially written into said input data word insertion location of said input data word queue.

24. A data communication controller formed on a single integrated circuit chip, for use in a local area network having a communication medium and a network communication protocol and being interfaceable with an external system bus including an external system data bus and an external system address bus, said external system data bus and said external system address bus being operably associated with a host processor and external buffer memory including a plurality of memory storage elements for buffering data packets including transmit packets and receive packets, and each said transmit packet and said receive packet being composed of one or more data words, said data communication controller comprising:

data communication means, operably interfaceable with said communication medium, for transmitting transmit packets over said communication medium and receiving receive packets from over said communication medium, said data communication means further including

a transmit data word queue for buffering the data words associated with one or more said transmit packets to be transmitted over said communication medium, and

a receive data word queue for buffering the data words of one or more said receive packets received from over said communication medium;

system bus interface means for interfacing said data communication controller with said external system bus, said system bus interface means further including

an input data word queue for buffering the data words transferred from said host processor over said external system bus to said data communication controller, and

an output data word queue for buffering data words to be transferred from said data communication controller over said external system bus to said external buffer memory;

first data transfer means for transferring data words along a second data channel defined from said input data word queue to said transmit data word queue;

second data transfer means for transferring data words along a second data channel defined from said receive data word queue to said output data word queue;

third data transfer means for transferring data words along a third data channel defined from said input data word queue to said internal data storage memory;

fourth data transfer means for transferring data words along a fourth data channel defined from said internal data storage memory to said output data word queue;

memory access control means for directly controlling access to memory storage elements in said external buffer memory, said memory access control means further including

first means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said transmit data word queue,

second means for controlling the transfer of data words from said receive data word queue to said output data word queue and thence to said external data buffer memory,

third means for controlling the transfer of data words from said external data buffer memory to said input data word queue and thence to said internal data storage memory,

fourth means for controlling the transfer of data words from said internal data storage means to said output data word queue and thence to said external buffer memory, and

an external address queue for buffering a plurality of said external addresses, said external address queue including a plurality of address storage locations for buffering said plurality of said external addresses,

an address insertion location for insertion of each said external address into said external address queue,

an address removal location operably associated with said external address system bus, for removal of each said external address from said external address queue and placement on said external system address bus, and

a first tag bit sequence queue having a first plurality of tag bit sequence storage locations for storage of a first plurality tag bit sequences, each said first tag bit sequence storage location being associated with one said address storage location, and said first tag bit sequence queue further having

a first tag bit sequence insertion location for insertion of each tag bit sequence into said first tag bit sequence queue, and

a first tag bit sequence removal location for removal of each said tag bit sequence from said first tag bit sequence queue;

a first processing means operably associated with said data communication means, for selectively processing said receive packets so as to perform said network communication protocol at said data communication controller; and

a second processing means independent of said first processing means, operably connected to said memory access control means, and including

means for managing the transfer of receive packets from said data communication means to said system bus interface means, and from said system bus interface means to said external buffer memory for storage therein, and

means for managing the transfer of transmit packets from said external buffer memory to said system bus interface means and from said system bus interface means to said data communication means, for transfer to said communication medium.

25. The data communication controller of claim 24, wherein said memory access control means further comprises:

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said first tag bit sequence insert location of said first tag bit sequence queue, wherein each said tag bit sequence is associated with one said external address and indicative of one of said first, second, third and fourth data channels within said data communication controller over which a corresponding data word is to be transferred under the direct control of said memory access control means.

26. The data communication controller of claim 24, wherein said input data word queue comprises:

a plurality of input data word storage locations for buffering a plurality of data words providable from said external buffer memory;

an input data word insertion location operably associated with said external system data bus, for insertion of each said data word into said input data word queue; and

an input data word removal location operably associated with said first data transfer means and third data transfer means, for removal of each said input data word from said input data word queue, and wherein said output data word queue comprises;

an plurality of output data word storage locations for buffering a plurality of data words provided from one of said receive data word queue and said internal data storage memory,

an output data word insertion location operably associated with said second data transfer means and said fourth data transfer means, for insertion of each said data word into said output data word queue, and

an output data word removal location operably associated with said external system data bus for removal of each said data word from said output data word queue.

27. The data communication controller of claim 26, wherein said input data word queue further comprises:

a second tag bit sequence queue having a second plurality of tag bit sequence storage locations for storage of a second plurality of tag bit sequences, each said tag bit storage location being associated with one said input data word storage location, and said second tag bit sequence queue further having

a second tag bit sequence insertion location for insertion of each said tag bit sequence into said second tag bit sequence queue, and

a second tag bit sequence removal location for removal of each said tag bit sequence from said second stage bit sequence queue; and

means for transferring each said tag bit sequence from said first tag bit sequence queue to said second tag bit sequence insertion location.

28. The data communication controller of claim 27, wherein said memory access control means further comprises:

pointer generating means for generating and sequentially incrementing address pointers which define

(i) the address insertion and removal locations of said external address queue,

(ii) the first tag bit sequence insertion and removal locations of said first tag bit sequence queue,

(iii) the input data word insertion and removal locations of said input data word queue,

(iv) the second tag bit sequence insertion and removal locations of said second tag bit sequence queue, and

(v) the output data word insertion and removal locations of said output data word queue.

29. The data communication controller of claim 28, wherein said memory access control means further comprises:

a first internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory into which data words are to be sequentially read from said output data word queue; and

a second internal address counter for incrementally generating from a preselected internal address, a sequence of internal addresses specifying the location of a sequence of data storage elements in said internal data storage memory from which data words are to read and sequentially written into said input data word insertion location of said input data word queue.

30. A data communication controller formed on a single integrated circuit chip, for use in a local area network having a communication medium and a network communication protocol, and being interfaceable with an external system bus including an external system data bus and an external system address bus each being operably associated with a host processor and external buffer memory having a plurality of memory storage elements for buffering data packets including transmit packets and receive packets, and each said transmit packet and said receive packet being composed of one or more data words, said data communication controller comprising:

data communication means, operably interfaceable with said communication medium, for transmitting transmit packets over said communication medium and receiving receive packets from over said communication medium, said data communication means further including

transmit packet assembling and transmitting means for assembling and transmitting the data words associated with each said transmit packet,

a transmit data word queue for buffering the data words associated with one or more said transmit packets to be transmitted over said communication medium,

receive packet receiving means for receiving the data words associated with each said receive packet, and

a receive data word queue for buffering the data words of one or more said receive packets received from over said communication medium;

system bus interface means for interfacing said data communication controller with said external system bus, said system bus interface means further including

an input data word queue for buffering the data words to be transferred from said host processor over said external system bus to said data communication controller, and

an output data word queue for buffering data words to be transferred from said data communication controller over said external system bus to said external buffer memory;

first data transfer means for transferring data words along a first data channel defined from said input data word queue to said transmit data word queue;

second data transfer means for transferring data words along a second data channel defined from said receive data word queue to said output data word queue;

a third data transfer means for transferring data words along a third data channel defined from said input data word queue to said internal data storage memory;

a fourth data transfer means for transferring data words along a fourth data channel defined from said internal data storage memory to said output data word queue;

a first asynchronous RISC-type processing means operably associated with said data communication means, and having

means for independently accessing said external buffer memory, and

means for selectively processing said receive packets so as to perform said network communication protocol at said data communication controller; and

a second asynchronous RISC-type processing means independent of said first synchronous RISC-type processing means, and including

means for independently accessing said external buffer memory,

means for managing the transfer of receive packets from said data communication means to said system bus interface means, and from said system bus interface means to said external buffer memory for storage therein, and

means for managing the transfer of transmit packets from said external buffer memory to said system bus interface means and from said system bus interface means to said data communication means, for transfer to said communication medium.

31. The data communication controller of claim 30, wherein said transmit data word queue comprises:

a plurality of transmit data word storage locations for buffering a plurality of data words provided from said input data word queue;

a transmit data word insertion location operably associated with said first data transfer means;

a transmit data word removal location operably associated with said transmit packet assembling and transmission means;

a tag bit sequence queue having a plurality of tag bit sequence storage locations for storage of a plurality of tag bit sequences, each said tag bit sequence storage location being associated with one said transmit data word storage location, and said tag bit sequence queue further having

a tag bit sequence insertion location for insertion of each said tag bit sequence into said tag bit sequence queue, and

a tag bit sequence removal location for removal of each said tag bit sequence from said tag bit sequence queue; and

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said tag bit sequence insertion location of said tag bit sequence queue,

wherein each said tag bit sequence is associated with one said data word in said transmit data word queue and is indicative of a transmit data word condition selected from the group consisting of (i) identifying the end of one said transmit packet, (ii) identifying the location of data bits in said associated data word, and (iii) identifying that no data is present said associated data word.

32. The data communication controller of claim 30, which further comprises:

transmit request arbitration means for arbitrating requests from said first RISC-type processing means and said second RISC-type processing means, to control said transmit data word queue and said transmit packet assembling and transmitting means so as to transmit one or more transmit packets from said transmit packet assembling and transmitting means.

33. The data communication controller of claim 32, wherein said transmit request arbitration means comprises

first logic circuitry in which said first RISC-type processing means can acquire unconditional access to said transmit data word queue and said transmit packet assembling and transmitting means, and

second logic circuitry in which said second RISC-type processing means can acquire conditional access to said transmit data word queue and said transmit packet assembling and transmitting means, and third logic circuitry in which said first RISC-type processing means acquires conditional access to said transmit data word queue and said transmit packet assembling and transmitting means.

34. The data communication controller of claim 31, wherein said transmit packet assembling and transmitting means comprises

means for reading tag bit sequences from said tag bit sequence and using said tag bit sequences to determine the location of each transmit packet in said transmit data word queue, and

means for transferring transmit data words from said transmit data word queue into a sequence of data bits in transmit data bit queue, for subsequent transmission over said communication medium.

35. The data communication controller of claim 34, wherein said transmit packet assembling and transmitting means comprises

transmit control means for receiving a transmit packet command from either said first RISC-type processing means or said second processing means, and

means, responsive to said received transmit command, for transmitting the data bits of each said determined transmit packet, over said communication medium.

36. The data communication controller of claim 35, wherein said transmit data word queue further comprises

pointer management means for generating and sequentially incrementing address pointers which define said transmit data word insertion and removal locations in said transmit data word queue, and said tag bit sequence insertion and removal locations of said tag bit sequence queue.

37. The data communication controller of claim 36, wherein said transmit data word queue comprises a first FIFO buffer, said receive data word queue comprises a second FIFO buffer, an input data word queue comprises a third FIFO buffer, and said output data word queue comprises a fourth FIFO buffer.

38. The data communication controller of claim 30, wherein said receive data word queue further comprises:

a plurality of receive data word storage locations for buffering receive data words provided from said receive packet receiving means,

a receive data word insertion location operably associated with said receive packet receiving means,

a first receive data word removal location operably associated with said first RISC-type processing means by a first internal system bus,

a second receive data word removal location operably associated with said second data processing means by a second internal system bus, and with said output data word queue by said second data transfer means, and

a tag bit sequence queue having a plurality of tag bit sequence storage locations for storage of a plurality of tag bit sequences, each said tag bit sequence storage locations being associated with one said receive data word storage location, and said tag bit sequence queue further having

a tag bit sequence insertion location for insertion of each said tag bit sequence queue, and

a tag bit sequence removal location for removal of each said tag bit sequence from said tag bit sequence queue.

39. The data communication controller of claim 38, wherein said receive packet receiving means further comprises:

means for analyzing the bits of receive packet; and

tag bit sequence generating means for generating one said tag bit sequence at a time and inserting said tag bit sequence into said tag bit sequence insertion location of said tag bit sequence queue, and

wherein each said tag bit is associated with one said data word in said receive data word queue and indicates the receive packet to which said data word is associated.

40. The data communication controller 39, which further comprises:

a first receive packet filtering means, operably associated with said first receive data word removal location, for determining the beginning and end of each receive packet being transferred though said receive data word queue and for determining whether each said receive packet is to be made accessible to said first RISC-type processing means by way of said first internal system bus.

41. The data communication controller of claim 40, which further comprises

a second receive packet filtering means, operably associated with said second receive data word removal location, for determining the beginning and end of each receive packet being transferred through said receive data word queue, and for determining whether each said receive packet is to be made accessible to said second RISC-type processing means by way of said second internal system bus.

42. The data communication controller of claim 40, wherein said first receive packet filtering means comprises

means for analyzing tag bit sequence in said tag bit sequence queue so as to determine the beginning and end of each said receive packet being transferred through said receive data word queue and whether each said receive packet is to be made accessible to said first RISC-type processing means.

43. The data communication controller of claim 42, wherein said second receive packet filtering means comprises

means for analyzing tag bit sequences in said tag bit sequence so as to determine the beginning and the end of each said receive packet being transferred through said receive data word queue and whether each said receive packet is to be made accessible to said second RISC-type processing means.

44. The data communication controller of claim 43, wherein said receive packet receiving means further comprises

first pointer generating means for generating and sequentially incrementing address pointers which define said receive data word insertion location in said receive data word queue, and wherein said first receive packet filtering means further comprises

a second pointer generating means for generating and sequentially incrementing address pointers which define said first receive data, word removal location in said receive data word queue.