Electronically configurable connection device

• US 5,434,982 A
• Filed: 06/12/1991
• Issued: 07/18/1995
• Est. Priority Date: 06/12/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Calzi, Philippe
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/714,197
• Time in Patent Office: 1,497 Days
• Field of Search: 395/725, 395/325, 395/275, 395/425, 364/246.3, 364/247.2, 364/280.2, 364/DIG. 1, 364/940.71, 364/DIG. 2
• US Class Current: 710/104
• CPC Class Codes: G06F 12/0669 with decentralised address assignment
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

The use of electromechanical devices for the configuration of the address for access to a peripheral unit in a data-processing system is avoided by replacing them with a non-volatile EEPROM-type memory. The dam in non-volatile memory is read as soon as the peripheral unit is put into operation, and the information that it delivers is stored in volatile memory and used as a comparison address to validate the operation of the peripheral unit.

Claims

1. An electronic connection device to connect a peripheral unit which includes a microprocessor through a bus to a central processing unit, said device comprising

an EEPROM-type memory memorizing a logic state which defines an access address of the peripheral unit;

said memory being connected to be programmed by the microprocessor of this peripheral unit,

wherein said memory is connected to an automatic starting-up circuit which is connected and configured to read the logic state of said memory as soon as power is applied to the peripheral unit, and

wherein the device includes a writing selection circuit for the selection, in writing mode, of said memory, said writing selection circuit being addressable by said central processing unit through said bus; and

wherein the memory is connected, firstly, to a set of flip-flop circuits and, secondly, to an end-of-reading circuit to prevent the deterioration of the memory.

2. A device according to claim 1, wherein said writing selection circuit is controlled by a circuit for the management of the peripheral circuit.

3. An electronic connection device to connect a peripheral unit through a bus to a central processing unit, said device being mountable on the peripheral unit and comprising

a plurality of non-volatile memory cells for electronically memorizing a logic state which defines an access address of said peripheral unit,

a plurality of volatile memory cells operatively connected to automatically copy the logic state of said non-volatile memory cells whenever power is applied to the peripheral unit after a power-down condition,

said volatile memory cells being connected to a validation circuit which is configured to compare the logic state of said volatile memory cells with an address transmitted to said validation circuit from said central processing unit and to produce a validation signal when the logic state of said volatile memory cells is the same as the transmitted address, to thereby provide access from the central processing unit to said peripheral unit through said bus upon the occurrence of said validation signal.

4. An electronic connection device in accordance with claim 3, further comprising

a selection circuit for the selection, in writing mode, of said plurality of non-volatile memory cells, said selection circuit being addressable by said central processing unit through said bus to program said plurality of non-volatile memory cells.

5. An electronic connection device in accordance with claim 3, further comprising

an automatic starting-up circuit connected and configured to read the logic state from said plurality of non-volatile memory cells as soon as the voltage is turned on in said peripheral unit.

6. An electronic connection device in accordance with claim 3, wherein each of said non-volatile memory cells is an EEPROM-type memory cell comprising a memory transistor having a conduction channel, a control gate, and a floating gate interposed between said control gate and said conduction channel thereof.

7. An electronic connection device in accordance with claim 6, further comprising a plurality of reading amplifiers corresponding in number to said plurality of non-volatile memory cells, each of said reading amplifiers being connected to the conduction channel of a respective one of said plurality of non-volatile memory cells and through a switch to a voltage source.

8. An electronic connection device in accordance with claim 7 wherein said switch is activated by said peripheral unit being turned on.

9. An electronic connection device in accordance with claim 6, further comprising

a plurality of flip-flop circuits corresponding in number to said plurality of non-volatile memory cells,

a plurality of pass transistors, each of said pass transistors having a conduction channel and a gate, the conduction channel of a respective pass transistor being connected between a respective memory cell and an input of a respective one of said plurality of flip-flop circuits, and an end-of-reading circuit for applying an end-of-reading signal to the gate of each of said pass transistors.

10. An electronic connection device in accordance with claim 9, further comprising

an additional pass transistor having a conduction channel and a gate, and

a plurality of reading amplifiers corresponding in number to said plurality of non-volatile memory cells, each of said reading amplifiers being connected to the conduction channel of a respective one of said plurality of non-volatile memory cells and through the conduction channel of said additional pass transistor and a switch to a voltage source, and

wherein said end-of-reading circuit applies said end-of-reading signal to the gate of said additional pass transistor.

11. An electronic connection device in accordance with claim 10, wherein said end-of-reading circuit comprises a monostable circuit which produces said end-of-reading signal responsive to the expiration of a time period.

12. An electronic connection device in accordance with claim 6 further comprising a source of programming voltages, a plurality of selection transistors corresponding in number to said plurality of memory transistors, each of said selection transistors having a conduction path and a control gate, the conduction path of each selection transistor being connected between a control gate of a respective memory transistor and said source of programming voltages, and a circuit for applying a selection signal to the control gate of each of said selection transistors to permit the passage of the programming voltages from said source of programming voltages through the selection transistors to the control gates of the memory transistors.

13. An electronic connection device in accordance with claim 12, further comprising

a plurality of flip-flop circuits corresponding in number to said plurality of non-volatile memory cells, a plurality of pass transistors, each of said pass transistors having a conduction channel and a gate, the conduction channel of a respective pass transistor being connected between a respective non-volatile memory cell and an input of a respective one of said plurality of flip-flop circuits, and an end-of-reading circuit for applying an end of reading signal to the gate of each of said pass transistors.

14. An electronic connection device in accordance with claim 13, further comprising

an additional pass transistor having a conduction channel and a gate, and a plurality of reading amplifiers corresponding in number to said plurality of non-volatile memory cells, each of said reading amplifiers being connected to the conduction channel of a respective one of said plurality of non-volatile memory cells and through the conduction channel of said additional pass transistor and a switch to a voltage source, and wherein said end-of-reading circuit applies said end-of-reading signal to the gate of said additional pass transistor.