Process for forming implanted regions with lowered channeling risk on semiconductors

• US 5,436,177 A
• Filed: 08/12/1993
• Issued: 07/25/1995
• Est. Priority Date: 08/19/1992
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Zaccherini, Chiara
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/106,037
• Time in Patent Office: 712 Days
• Field of Search: 437/27, 437/46, 437/47, 437/60, 437/918, 148/DIG. 136
• US Class Current: 438/385
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

Claims

1. A process for forming implanted regions on semiconductor devices with lowered channelling risk, wherein the semiconductor electronic devices include at least one layer of polycrystalline silicon which covers at least two isolation regions and an active area liable to a channelling phenomena, comprising the steps of:

depositing a masking layer on said isolation regions covered by said polycrystalline layer;

implanting a first dopant species, in any unmasked areas of the semiconductor devices, to amorphousize any unmasked polycrystalline silicon areas;

removing the masking layer; and

implanting a second dopant species over the entire polycrystalline silicon layer to form resistors over the isolation regions.

2. The process according to claim 1, wherein the first dopant species is an N-type dopant.

3. The process according to claim 1, wherein the second dopant species is a P-type dopant.

4. The process according to claim 1, wherein an implant dosage of the first dopant implanting step is within the range from 5×

10¹⁴ to 1×

10¹⁶ ions/cm².

5. The process according to claim 1, wherein an implant dosage of the second dopant implanting step is within the range from 1×

10¹² to 1×

10¹⁵ ions/cm².

6. The process according to claim 1, wherein the masking step is performed using a photoresist layer.

7. The process according to claim 1, wherein the first dopant implanting step is carried out using arsenic ions.

8. The process according to claim 1, wherein the first dopant implanting step is carried out using phosphorous ions.

9. The process according to claim 1, wherein the second dopant implanting step is carried out using boron ions.

10. The process according to claim 1, wherein the claimed steps are performed in sequence.

11. The process according to claim 1, wherein the first dopant species is a P-type dopant.

12. The process according to claim 1, wherein the second dopant species is an N-type dopant.

13. The process according to claim 11, wherein the first dopant species comprises boron ions.

14. The process according to claim 12, wherein the second-dopant species comprises phosphorous ions.