High performance gaas devices and method

• US 5,436,499 A
• Filed: 03/11/1994
• Issued: 07/25/1995
• Est. Priority Date: 03/11/1994
• Status: Expired due to Term

• Current Assignee: Masimo Semiconductor Inc. (Masimo Corporation)
• Original Assignee: Spire Corporation
• Inventors: Kalkhoran, Nader M., Namavar, Fereydoon
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US08/212,115
• Time in Patent Office: 501 Days
• Field of Search: 257/617, 257/604, 257/608, 257/513, 257/509, 257/147, 257/524
• US Class Current: 257/617
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/2654 in AIIIBV compounds
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/3228 of AIIIBV compounds, e.g. to make them semi-insulating
• CPC Class Codes: H01L 21/7605 between components manufactured in an active substrate comprising AIII BV compounds
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/8126 Thin film MESFET's
• CPC Class Codes: H01S 5/0262 Photo-diodes, e.g. transceiver devices, bidirectional devices H01S5/0265 takes precedence
• CPC Class Codes: H01S 5/18305 with emission through the substrate, i.e. bottom emission
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/18358 containing spacer layers to adjust the phase of the light wave in the cavity
• CPC Class Codes: H01S 5/2063 obtained by particle bombardment
• CPC Class Codes: H01S 5/3432 the whole junction comprising only (AI)GaAs

Abstract

High performance GaAs and AlGaAs-based devices and a process enabling the manufacture of new III-V compound technologies are disclosed. The GaAs devices are particularly useful as VLSICs by possessing a high degree of electrical insulation, both vertical and lateral, between closely packed active devices. Essentially, the GaAs devices include a substrate on which is formed, preferably by epitaxial growth or by ion implantation, an active GaAs, or AlGaAs region incorporating, by appropriate doping, the simultaneously therein formed active segments. The active segments are electrically shielded by providing insulating stratums in the active GaAs, AlGaAs region surrounding the active segments. Preferably, the insulating stratums are formed therein by implanting arsenic ions therein so as to form arsenic precipitates. Preferably, a passivated surface layer also is formed in part of the surface of the GaAs, AlGaAs active layer, also preferably by implanting arsenic ions therein. Following implantation, the GaAs, AlGaAs devices are annealed in a reactor preferably at a temperature of about 600° C. in an arsine ambient gas for a period of about 10 minutes.

Claims

1. A III-V compound-based device comprising:

(a) a substrate;

(b) an active region grown on said substrate and incorporating the active segments of said device; and

(c) an insulating stratum formed in said active region adjacent said substrate;

(d) said stratum comprising a plurality of arsenic precipitates formed therein;

(e) said plurality of arsenic precipitates containing an excess arsenic in a range from about one to about 1.5 atomic percent.

2. The device of claim 1 wherein said device is one of a group consisting of:

MESFETs, HEMTs, MISFETs, inverter circuits and tunable wavelength vertical cavity emitting lasers.

3. The device of claim 1 wherein said substrate is one of a group cosisting of:

a GaAs, AlGaAs, AlGaAs-on-GaAs, Ge, GaAs-on-Ge, Si, GaAs-on-Si, GaAs-on-Ge-on-Si, and Silicon-on-Insulator or GaAs on Silicon-on-Insulator substrate.

4. The device of claim 1 wherein said active region is an epitaxially grown layer.

5. The device of claim 1 wherein said active region is a GaAs region and further including side insulating stratums formed in part of the surface of said GaAs active region normal to said insulating stratum formed adjacent said substrate, said side insulating stratums surrounding said active segments of said device, and further including an insulating stratum formed in part of the surface of said GaAs active region and in operative association with at least one of said active segments of said device.

6. The device of claim 5 wherein said insulating stratum shields said device from backgating and sidegating effects for the entire length of use of said device by maintaining the drain current of said device constant despite the application of negative bias to its ohmic contact and by eliminating cross-talk with adjacently placed devices.

7. The device of claim 5 wherein each of said insulating stratums is formed in said device by implanting arsenic ions into said GaAs active region with an arsenic dose ranging from about 1×

10¹⁵ to about 1×

10¹⁷ As⁺ ions/cm² at energies between about 50 keV and 3 MeV, followed by annealing at about 600°

C. in an ambient arsine gas for a time period of about 10 minutes.

8. A GaAs device for use as a very large scale GaAs integrated circuit, said device comprising:

(a) a substrate formed of one of a group consisting of;

a GaAs, AlGaAs, AlGaAs-on-GaAs, Ge, GaAs-on-GE, Si, GaAs-on-Si, GaAs-on-Ge-on-Si, Silicon-on-Insulator, and GaAs on Silicon-on-Insulator substrate;

(b) an active region epitaxially grown on said substrate, said active region incorporating the active segments of said device;

(c) insulating stratums formed in said active region and surrounding said active segments, said insulating stratums providing both lateral and vertical electrical insulation to said device to eliminate backgating and sidegating effects of said device;

(d) said insulating stratums being formed by implanting excess arsenic ions in a range from about one to about 1.5 atomic percent into said active region, followed by anneal; and

(e) a passivated surface layer formed in the surface of said active region in operative association with at least one of said active segments.

9. The GaAs device of claim 8 wherein said device is one of a group consisting of:

MESFETs, HEMTs, MISFETs, inverter circuits and tunable wavelength vertical cavity emitting lasers.

10. The GaAs device of claim 8 wherein said implantation of arsenic ions is effected with a dose ranging from about 1×

10¹⁵ to about 1×

10¹⁵ As⁺ ions/cm² at energies of at least about 180 keV, wherein said anneal is effected at a temperature of about 600°

C. in an ambient arsine gas for a time period of about 10 minutes.