Computer controlled cable tester

• US 5,436,554 A
• Filed: 09/04/1992
• Issued: 07/25/1995
• Est. Priority Date: 09/04/1992
• Status: Expired due to Fees

• Current Assignee: Harold J. Decker Jr
• Original Assignee: Harold J. Decker Jr
• Inventors: Decker, Harold J. Jr.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): TOBIN, C
• Application Number:
  US07/940,490
• Time in Patent Office: 1,054 Days
• Field of Search: 324/66, 324/73.1, 324/538, 324/539, 324/540, 324/542, 379/25, 379/26
• US Class Current: 324/66
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G01R 31/58 Testing of lines, cables or conductors testing of electric windings G01R31/72
• CPC Class Codes: G01R 31/60 Identification of wires in a multicore cable

Abstract

A device for determining interconnections between terminal positions at opposite ends of cable includes a test circuit, connectors for connecting the test circuit to the terminal positions of the cable and a connector for interfacing the test circuit with a computer. The test circuit sequentially selects each of the terminal positions of the cable as a test point and includes a demultiplexing/multiplexing device for applying a test voltage to the selected terminal position, a resistor for maintaining a load resistance effective to provide a second logic signal at each terminal position other than the terminal position as the test point to which the test voltage is applied and to maintain a first logic signal at each terminal position to which the test voltage is not applied, a memory device for storing the logic signal present at each terminal position during application of the test voltage to the selected test point terminal position, and the demultiplexing/multiplexing device for determining, subsequent to removal of the test voltage from the test point, the logic signals stored by the memory device for each terminal position. A stored first logic signal is indicative of a terminal position not having a common connection with the test point and a stored second logic signal is indicative of a terminal position having a common connection with the test point. A method for determining interconnections between terminal positions at opposite ends of a cable includes operating the above described device.

Claims

1. A device for determining interconnections between terminal positions at opposite ends of a cable, comprising:

means for testing said terminal positions, comprising;

means for initializing said terminal positions with a first logic signal;

demultiplexing means for sequentially selecting each terminal position as a test point and applying a test voltage thereto;

resistor means for applying a load resistance effective to maintain a second logic signal at each terminal position having the test voltage thereon and to maintain the first logic signal at each terminal position not having the test voltage thereon;

memory means for storing the logic signals present at all terminal positions during application of the test voltage to the test point; and

multiplexing means for determining subsequent to removal of the test voltage from the test point the logic signal stored at the memory means for each terminal position, a stored first logic signal being indicative of a terminal position not having a common connection with the test point and a stored second logic signal being indicative of a terminal position having a common connection with the test point;

connector means for connecting said means for testing with said terminal positions; and

interface means for interfacing with a computer.

2. The device of claim 1 wherein said demultiplexing means and said multiplexing means comprise a multiplexer/demultiplexer integrated circuit.

3. The device of claim 2 wherein said multiplexer/demultiplexer integrated circuit comprises a CMOS 4051 integrated circuit.

4. The device of claim 1 wherein said memory means comprises a flip-flop circuit.

5. The device of claim 4 wherein said flip-flop circuit comprises a plurality of tri-state D flip-flops each having an input and an output connected together and connected to a corresponding terminal position.

6. The device of claim 1 wherein said demultiplexing means and said multiplexing means comprise a plurality of multiplexer/demultiplexer integrated circuits;

and

further comprising;

means for selecting one of said plurality of multiplexer/demultiplexer integrated circuits.

7. The device of claim 6 wherein said means for selecting comprises a decoder integrated circuit.

8. The device of claim 1 further comprising:

adapter means for connecting between said connector means and the ends of the cable.

9. A method for determining interconnections between terminal positions at opposite ends of a cable, comprising the steps of:

initializing the terminal positions with a first logic signal,

sequentially selecting each terminal position as a test point and applying a test voltage thereto, while a load resistance effective to maintain a second logic signal at each terminal position having the test voltage thereon and to maintain the first logic signal at each terminal position not having the test voltage thereon is applied;

storing the logic signals present at all terminal positions during application of the test voltage to the test point; and

determining, subsequent to removal of the test voltage from the test point, the logic signal stored for each terminal position, wherein a first logic signal is indicative of a terminal position not having a common connection with the test point and a stored second logic signal is indicative of a terminal position having a common connection with the test point.

10. The method of claim 9 wherein said step of sequentially selecting and said step of determining comprise sequentially selecting and determining using a multiplexer/demultiplexer integrated circuit.

11. The method of claim 10 wherein said multiplexer/demultiplexer integrated circuit comprises a CMOS 4051 integrated circuit.

12. The method of claim 9 wherein said step of storing comprises storing the logic signal using a flip-flop circuit.

13. The method of claim 12 wherein said flip-flop circuit comprises a plurality of tri-state D flip-flops each having an input and an output connected together and connected to a corresponding terminal position.

14. The method of claim 9 wherein said step of sequentially selecting and said step of determining comprise sequentially selecting and determining using a plurality of multiplexer/demultiplexer integrated circuits;

and

further comprising the step of;

selecting one of said plurality of multiplexer/demultiplexer integrated circuits.

15. The method of claim 14 wherein said step of selecting comprises selecting using a decoder integrated circuit.

16. The method of claim 9 further comprising the step of:

connecting between said connector means and the ends of the cable using adapter means.