Remote control signal processing circuit for a microcomputer

• US 5,436,853 A
• Filed: 07/28/1994
• Issued: 07/25/1995
• Est. Priority Date: 07/24/1991
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Shimohara, Kazunari
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): CHOI, KYLE JAEHUN
• Application Number:
  US08/281,656
• Time in Patent Office: 362 Days
• Field of Search: 364/569, 364/486, 364/574, 358/194.1, 340/825.63, 359/142, 359/146, 375/22
• US Class Current: 702/79
• CPC Class Codes: G08C 19/28 using pulse code
• CPC Class Codes: G08C 25/00 Arrangements for preventing or correcting errors; Monitoring arrangements
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit

Abstract

A remote control signal processing circuit uses hardware to check the pulse of the remote control signal, detect the leader code, and make "0" or "1" judgment for status code or data code. Based on the edge detection signals given by the edge detection circuit to detect the leading and trailing edges of the signal, the pulse width of the remote control signal is measured with a timer, and the measurement value of the pulse width is latched by a latch circuit. A check circuit compares the value latched at the latch circuit with the criteria stored in the register in advance for normal/abnormal judgment of pulse width and outputs a pulse error signal when they are not identical. Alternatively, the circuit may be provided with registers to store in advance criteria for logical "0" or "1" based on the pulse width of the remote control signal so that a judgment circuit compares the measurement value of the pulse width in the latch circuit and the criteria in the registers to judge whether the logical value is "0" or "1".

Claims

1. A remote control signal processing circuit for a microcomputer comprising:

means for receiving a remote control signal and producing a pulse signal indicative thereof;

an edge detection means for detecting rising and falling of said pulse signal and generating a first output signal which becomes active level at every occurrence of one of the leading edge or the trailing edge of said pulse signal and a second output signal which becomes active level at every occurrence of the other of the leading edge or the trailing edge of said pulse signal;

a timer counter for counting clock pulses and generating a counter value corresponding to a number of clock pulses counted;

a first latch means for receiving said first output signal, sampling and holding the counter value of said timer counter at every occurrence of switching of said first output signal into the active level, and for resetting said counter value of said timer counter to an initial value;

a second latch means for receiving said second output signal, sampling and holding the counter value of said timer counter at every occurrence of switching of said second output signal into an active state;

a comparing register temporarily storing a programmable predetermined value; and

comparing means for comparing the value provided to said second latch means and the value stored in said comparing register, and generating a detection signal indicative that the pulse width of said pulse signal is other than the predetermined value when the compared values are mutually different from each other.

2. A remote control signal processing circuit as set forth in claim 1, wherein said first and second latch means generate a first control signal every time of sampling and holding the counter value of said timer counter, and holding the counter value of said timer counter, said comparing means including:

a comparator generating a comparator output signal which becomes a first logical level when the values of said second latch circuit and said comparing register are matched with each other and a second logical level otherwise; and

a gate circuit masking said first control signal when said comparator output signal is in said first logical level or outputting said first control signal as a detection signal when said comparator output signal is in said second logical level.

3. A remote control signal processing circuit as set forth in claim 2, further comprising a central processing unit (CPU) generating said programmable predetermined value and storing the same in said comparing register.

4. A remote control signal processing circuit as set forth in claim 3, wherein said first latch means generates a second control signal every time of sampling and holding the counter value of said timer counter for resetting said timer register, and said first and second control signals are supplied to said CPU.

5. A remote control signal processing circuit as set forth in claim 1, which further comprises:

a first register for temporarily storing a programmable first reference value;

a second register for temporarily storing a programmable second reference value; and

means coupled with said first latch means and said first and second registers for generating a first data discrimination signal indicative that said pulse signal is in one of the states of data "0" or data "1" when the value of said first latch means is greater than or equal to said first reference value and less than or equal to said second reference value.

6. A remote control signal processing circuit as set forth in claim 5, which further comprises:

a third register temporarily storing a programmable third reference value;

a fourth register temporarily storing a programmable fourth reference value; and

means coupled with said first latch means and said third and fourth registers for generating a second data discrimination signal indicative that said pulse signal is in one of the states of data "0" [or data "1" when the value of said first latch means is greater than or equal to said third reference value and less than or equal to said fourth reference value.

7. A remote control signal processing circuit as set forth in claim 6, which further comprises a central processing unit (CPU) generating respectively said programmable predetermined value, said first, second, third and fourth reference values for writing in, and said detection signal and said first and second data discrimination signal are supplied to said CPU.